| Message ID | 20230612063429.3343061-4-bigunclemax@gmail.com (mailing list archive) |
|---|---|
| State | New |
| Delegated to: | Daniel Lezcano |
| Headers | show |
| Series | [v4,1/3] dt-bindings: thermal: sun8i: Add binding for D1/T113s THS controller | expand |
On Mon, Jun 12, 2023 at 09:34:19AM +0300, Maksim Kiselev wrote: > From: Maxim Kiselev <bigunclemax@gmail.com> > > This patch adds a thermal sensor controller node for the D1/T113s. > Also it adds a THS calibration data cell and thermal zone. > > Signed-off-by: Maxim Kiselev <bigunclemax@gmail.com> The RISC-V patchwork automation is complaining about this patch while running dtbs_check: arch/riscv/boot/dts/allwinner/sun20i-d1s-mangopi-mq.dtb: thermal-zones: cpu-thermal: 'trips' is a required property From schema: Documentation/devicetree/bindings/thermal/thermal-zones.yaml Cheers, Conor.
Hi, Conor пн, 12 июн. 2023 г. в 10:55, Conor Dooley <conor.dooley@microchip.com>: ... > The RISC-V patchwork automation is complaining about this patch while > running dtbs_check: > arch/riscv/boot/dts/allwinner/sun20i-d1s-mangopi-mq.dtb: thermal-zones: cpu-thermal: 'trips' is a required property > From schema: Documentation/devicetree/bindings/thermal/thermal-zones.yaml I didn't add 'trips' because I'm not sure if they should be the same for the D1 and the T113s. Maybe it's better to drop 'thermal-zones' from this patch and add them later in separate patches for T113s and D1?
On Mon, Jun 12, 2023 at 11:17:20AM +0300, Maxim Kiselev wrote: > Hi, Conor > > пн, 12 июн. 2023 г. в 10:55, Conor Dooley <conor.dooley@microchip.com>: > > ... > > > The RISC-V patchwork automation is complaining about this patch while > > running dtbs_check: > > arch/riscv/boot/dts/allwinner/sun20i-d1s-mangopi-mq.dtb: thermal-zones: cpu-thermal: 'trips' is a required property > > From schema: Documentation/devicetree/bindings/thermal/thermal-zones.yaml > > I didn't add 'trips' because I'm not sure if they should be the same > for the D1 and the T113s. I'm sorry, but I am of no help there. Perhaps some of the Allwinner devs can help you on that front. > Maybe it's better to drop 'thermal-zones' from this patch and add them > later in separate patches > for T113s and D1? Does it pass dtbs_check with the thermal-zones removed? Cheers, Conor.
пн, 12 июн. 2023 г. в 20:27, Conor Dooley <conor@kernel.org>: > > On Mon, Jun 12, 2023 at 11:17:20AM +0300, Maxim Kiselev wrote: > > Hi, Conor > > > > пн, 12 июн. 2023 г. в 10:55, Conor Dooley <conor.dooley@microchip.com>: > > > > ... > > > > > The RISC-V patchwork automation is complaining about this patch while > > > running dtbs_check: > > > arch/riscv/boot/dts/allwinner/sun20i-d1s-mangopi-mq.dtb: thermal-zones: cpu-thermal: 'trips' is a required property > > > From schema: Documentation/devicetree/bindings/thermal/thermal-zones.yaml > > > > I didn't add 'trips' because I'm not sure if they should be the same > > for the D1 and the T113s. > > I'm sorry, but I am of no help there. Perhaps some of the Allwinner devs > can help you on that front. > > > Maybe it's better to drop 'thermal-zones' from this patch and add them > > later in separate patches > > for T113s and D1? > > Does it pass dtbs_check with the thermal-zones removed? Yes, it passes.
diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index 922e8e0e2c09..b893f3325554 100644 --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi @@ -10,6 +10,7 @@ #include <dt-bindings/reset/sun8i-de2.h> #include <dt-bindings/reset/sun20i-d1-ccu.h> #include <dt-bindings/reset/sun20i-d1-r-ccu.h> +#include <dt-bindings/thermal/thermal.h> / { #address-cells = <1>; @@ -138,6 +139,19 @@ ccu: clock-controller@2001000 { #reset-cells = <1>; }; + ths: thermal-sensor@2009400 { + compatible = "allwinner,sun20i-d1-ths"; + reg = <0x02009400 0x400>; + interrupts = <SOC_PERIPHERAL_IRQ(58) IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_THS>; + clock-names = "bus"; + resets = <&ccu RST_BUS_THS>; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + status = "disabled"; + #thermal-sensor-cells = <0>; + }; + dmic: dmic@2031000 { compatible = "allwinner,sun20i-d1-dmic", "allwinner,sun50i-h6-dmic"; @@ -365,6 +379,10 @@ sid: efuse@3006000 { reg = <0x3006000 0x1000>; #address-cells = <1>; #size-cells = <1>; + + ths_calibration: thermal-sensor-calibration@14 { + reg = <0x14 0x4>; + }; }; crypto: crypto@3040000 { @@ -843,4 +861,12 @@ rtc: rtc@7090000 { #clock-cells = <1>; }; }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 0>; + }; + }; };