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signed) header.d=none;dmarc=none action=none header.from=oss.nxp.com; Received: from DU0PR04MB9417.eurprd04.prod.outlook.com (2603:10a6:10:358::11) by PAXPR04MB8943.eurprd04.prod.outlook.com (2603:10a6:102:20e::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6588.35; Thu, 20 Jul 2023 09:12:26 +0000 Received: from DU0PR04MB9417.eurprd04.prod.outlook.com ([fe80::c874:7c87:c13b:64f8]) by DU0PR04MB9417.eurprd04.prod.outlook.com ([fe80::c874:7c87:c13b:64f8%5]) with mapi id 15.20.6609.024; Thu, 20 Jul 2023 09:12:26 +0000 From: "Peng Fan (OSS)" To: ulf.hansson@linaro.org, shawnguo@kernel.org, s.hauer@pengutronix.de Cc: kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Peng Fan Subject: [PATCH V2 3/8] genpd: imx: scu-pd: add more PDs Date: Thu, 20 Jul 2023 17:16:56 +0800 Message-Id: <20230720091701.517197-4-peng.fan@oss.nxp.com> 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bpuWT1WffBTWxD0yUv+JhnEgYr6/7GimuzIi13WpD38TJWslS/+SoZccvqVmzTQaYPPJ1bTIAO7fxXTLESQ0qXgXrFaqIJbXxrDooH881f09A8BwYZrg8wBmwHM3nTwHIBFcQmPEKvhj3+IHRJyQYQPBuSPYUvni0aGbcyGRHruYqnRDxX+v7GTcJjT03+VI2vFGGP9O1RzpVSlMB1FOPcBCTP20KWOWeOzcR7+Zr+nxqDaCG3DkDgk4r9qhj83PgNu32MYfURE/NJ2EqVbfHeqbjlVxS1ITGBLXdCY3Ue+0dpSrSuoYpkA2/PtIB9n77/tKk31XxJ5fWQTMvtA+kVFIkMpPVbKWG154HXGF9tjlNpaCJykcdkQ204+FRUZdGqKgZiYbKrYiks7Bdn2io+l2Zzvme1M126LExTt/5vfkhbYncm4bsHkGaH+fm4C6R22UTsbGLjOXTvB338aAMnHCOce1BWqEHr+JF+GjhcP07bVZ5NSRTXoY7w4ZU8LOvbsc5Hlz+A7pQ+AhbwfP1yyqHf8sERnhvm58mJBsQabam7WLkwv2tiJ8sVigDlK2LMX9NWp7gCv6jvJS3rahUlX7ZRFCwqUyhLs/O6jCVo22bgjAfHLY8QwR0vuxJC3H1C3FXr3hPHKuLLRqH692fQOd3TekhptIEUfgloukObpWGMPq1LqqYSRM07xqYbxfUHa1KVJ3NGrDLqINB1pgsgCnDCC/MaBPssnTA6Vo2hUNNt5/STeaX67zXXwNo8l+FLexno5S4FdworqmZyycW1PB35Mg3n2eshtRHvVeiSvgz7SO/SPTjamQY+bjj+Q9SXtV7kGDmyT1tToRqU6xCxr6fk7fQYv8RzrkSYdb3g5U38hjz8YF7GziOnH4qxDgr04vg41QgmHpU6EQtcG7kwvUbVzWWPsSb414G/Kbgq0uD7pUJQuXObIYR/JyQKtuG/dBsPU9Zimyj8sfbmSe5AYZlB54RS0HOkLbCZzFqA53UIKQhGE54KwEgVAbCWEBMJdP4qJHIcS3SlLC1fJfhOtT8hbOm76LU5TEgktdI15TMWPxQMxKRA9oCAFoa7BAikN/7gJjZML2Tr3fkubbwU65Jlo/3vKO4fNijn+xMGXr/I2/lFBi7YmyLerpLZ88+PG+0UWyKlX2XY47qKuN9tKZ7qknqi0Uo8kO5XSFmOtoqumI0a1HLPbo2a7E/86O1udWSNR1YPbTfVqHQIbkpcyv+TKVv2jX+EZXiRRypj3nADYwQPhIuLmSwViP31C9hEgLrYs3RA++80mGclCEVp1iuw2L/5EamXofbLC4o5Cufh7z+VfxS67nUileHvBfaKsO4Q5kdeyEP8acd3TzjC6GDLh/2uNKTr5yVPtIHBxj8Xb6+rVJdDg2WIy+IseqqXNsTb9/p38wZao5wAgllnrzLPyv8vbuMjMbvF0tdZsHpD+b11JVlVMd/6Jc+ls/aYJ1qA+d1dbphjortrxcJ89B22x3fyOPkRQpARQg4WwikGivvgrxckhz7uGaxXYe5BmGhA/FVFTvq2N+q2ww/ZrrqVKOaQeeEeSH8Uxe7zEAH3YonWGuk22xgjRv6pbs X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 61b86f08-4ecd-4478-cc5c-08db89016f80 X-MS-Exchange-CrossTenant-AuthSource: DU0PR04MB9417.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jul 2023 09:12:26.3516 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: pG0XQNVFjNZkG4UJzApYIsBT1TJW7Tqyc1LirziTXVlDgBJWz9pZHD1TYwK+yFckcohnT7x9kWLYuiIrXNRlOQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR04MB8943 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Peng Fan Add more PDs for i.MX8QM and i.MX8DXL, including dma-ch, esai, gpu1, v2x-mu, seco-mu, hdmi, img and etc. Signed-off-by: Peng Fan --- drivers/genpd/imx/scu-pd.c | 65 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/drivers/genpd/imx/scu-pd.c b/drivers/genpd/imx/scu-pd.c index 5a28f5af592a..08583a10ac62 100644 --- a/drivers/genpd/imx/scu-pd.c +++ b/drivers/genpd/imx/scu-pd.c @@ -121,12 +121,16 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { { "audio-pll1", IMX_SC_R_AUDIO_PLL_1, 1, false, 0 }, { "audio-clk-0", IMX_SC_R_AUDIO_CLK_0, 1, false, 0 }, { "audio-clk-1", IMX_SC_R_AUDIO_CLK_1, 1, false, 0 }, + { "mclk-out-0", IMX_SC_R_MCLK_OUT_0, 1, false, 0 }, + { "mclk-out-1", IMX_SC_R_MCLK_OUT_1, 1, false, 0 }, { "dma0-ch", IMX_SC_R_DMA_0_CH0, 32, true, 0 }, { "dma1-ch", IMX_SC_R_DMA_1_CH0, 16, true, 0 }, { "dma2-ch", IMX_SC_R_DMA_2_CH0, 32, true, 0 }, + { "dma3-ch", IMX_SC_R_DMA_3_CH0, 32, true, 0 }, { "asrc0", IMX_SC_R_ASRC_0, 1, false, 0 }, { "asrc1", IMX_SC_R_ASRC_1, 1, false, 0 }, { "esai0", IMX_SC_R_ESAI_0, 1, false, 0 }, + { "esai1", IMX_SC_R_ESAI_1, 1, false, 0 }, { "spdif0", IMX_SC_R_SPDIF_0, 1, false, 0 }, { "spdif1", IMX_SC_R_SPDIF_1, 1, false, 0 }, { "sai", IMX_SC_R_SAI_0, 3, true, 0 }, @@ -146,8 +150,10 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { { "lpi2c", IMX_SC_R_I2C_0, 5, true, 0 }, { "adc", IMX_SC_R_ADC_0, 2, true, 0 }, { "lcd", IMX_SC_R_LCD_0, 1, true, 0 }, + { "lcd-pll", IMX_SC_R_ELCDIF_PLL, 1, true, 0 }, { "lcd0-pwm", IMX_SC_R_LCD_0_PWM_0, 1, true, 0 }, { "lpuart", IMX_SC_R_UART_0, 5, true, 0 }, + { "sim", IMX_SC_R_EMVSIM_0, 2, true, 0 }, { "lpspi", IMX_SC_R_SPI_0, 4, true, 0 }, { "irqstr_dsp", IMX_SC_R_IRQSTR_DSP, 1, false, 0 }, @@ -163,10 +169,15 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { /* GPU SS */ { "gpu0-pid", IMX_SC_R_GPU_0_PID0, 4, true, 0 }, + { "gpu1-pid", IMX_SC_R_GPU_1_PID0, 4, true, 0 }, + /* HSIO SS */ + { "pcie-a", IMX_SC_R_PCIE_A, 1, false, 0 }, + { "serdes-0", IMX_SC_R_SERDES_0, 1, false, 0 }, { "pcie-b", IMX_SC_R_PCIE_B, 1, false, 0 }, { "serdes-1", IMX_SC_R_SERDES_1, 1, false, 0 }, + { "sata-0", IMX_SC_R_SATA_0, 1, false, 0 }, { "hsio-gpio", IMX_SC_R_HSIO_GPIO, 1, false, 0 }, /* MIPI SS */ @@ -186,11 +197,20 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { { "lvds1-pwm", IMX_SC_R_LVDS_1_PWM_0, 1, false, 0 }, { "lvds1-lpi2c", IMX_SC_R_LVDS_1_I2C_0, 2, true, 0 }, + { "mipi1", IMX_SC_R_MIPI_1, 1, 0 }, + { "mipi1-pwm0", IMX_SC_R_MIPI_1_PWM_0, 1, 0 }, + { "mipi1-i2c", IMX_SC_R_MIPI_1_I2C_0, 2, 1 }, + { "lvds1", IMX_SC_R_LVDS_1, 1, 0 }, + /* DC SS */ { "dc0", IMX_SC_R_DC_0, 1, false, 0 }, { "dc0-pll", IMX_SC_R_DC_0_PLL_0, 2, true, 0 }, { "dc0-video", IMX_SC_R_DC_0_VIDEO0, 2, true, 0 }, + { "dc1", IMX_SC_R_DC_1, 1, false, 0 }, + { "dc1-pll", IMX_SC_R_DC_1_PLL_0, 2, true, 0 }, + { "dc1-video", IMX_SC_R_DC_1_VIDEO0, 2, true, 0 }, + /* CM40 SS */ { "cm40-i2c", IMX_SC_R_M4_0_I2C, 1, false, 0 }, { "cm40-intmux", IMX_SC_R_M4_0_INTMUX, 1, false, 0 }, @@ -205,11 +225,56 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { { "cm41-mu-a1", IMX_SC_R_M4_1_MU_1A, 1, false, 0}, { "cm41-lpuart", IMX_SC_R_M4_1_UART, 1, false, 0}, + /* CM41 SS */ + { "cm41_i2c", IMX_SC_R_M4_1_I2C, 1, false, 0 }, + { "cm41_intmux", IMX_SC_R_M4_1_INTMUX, 1, false, 0 }, + + /* DB SS */ + { "perf", IMX_SC_R_PERF, 1, false, 0}, + /* IMAGE SS */ { "img-jpegdec-mp", IMX_SC_R_MJPEG_DEC_MP, 1, false, 0 }, { "img-jpegdec-s0", IMX_SC_R_MJPEG_DEC_S0, 4, true, 0 }, { "img-jpegenc-mp", IMX_SC_R_MJPEG_ENC_MP, 1, false, 0 }, { "img-jpegenc-s0", IMX_SC_R_MJPEG_ENC_S0, 4, true, 0 }, + + /* SECO SS */ + { "seco_mu", IMX_SC_R_SECO_MU_2, 3, true, 2}, + + /* V2X SS */ + { "v2x_mu", IMX_SC_R_V2X_MU_0, 2, true, 0}, + { "v2x_mu", IMX_SC_R_V2X_MU_2, 1, true, 2}, + { "v2x_mu", IMX_SC_R_V2X_MU_3, 2, true, 3}, + { "img-pdma", IMX_SC_R_ISI_CH0, 8, true, 0 }, + { "img-csi0", IMX_SC_R_CSI_0, 1, false, 0 }, + { "img-csi0-i2c0", IMX_SC_R_CSI_0_I2C_0, 1, false, 0 }, + { "img-csi0-pwm0", IMX_SC_R_CSI_0_PWM_0, 1, false, 0 }, + { "img-csi1", IMX_SC_R_CSI_1, 1, false, 0 }, + { "img-csi1-i2c0", IMX_SC_R_CSI_1_I2C_0, 1, false, 0 }, + { "img-csi1-pwm0", IMX_SC_R_CSI_1_PWM_0, 1, false, 0 }, + { "img-parallel", IMX_SC_R_PI_0, 1, false, 0 }, + { "img-parallel-i2c0", IMX_SC_R_PI_0_I2C_0, 1, false, 0 }, + { "img-parallel-pwm0", IMX_SC_R_PI_0_PWM_0, 2, true, 0 }, + { "img-parallel-pll", IMX_SC_R_PI_0_PLL, 1, false, 0 }, + + /* HDMI TX SS */ + { "hdmi-tx", IMX_SC_R_HDMI, 1, false, 0}, + { "hdmi-tx-i2s", IMX_SC_R_HDMI_I2S, 1, false, 0}, + { "hdmi-tx-i2c0", IMX_SC_R_HDMI_I2C_0, 1, false, 0}, + { "hdmi-tx-pll0", IMX_SC_R_HDMI_PLL_0, 1, false, 0}, + { "hdmi-tx-pll1", IMX_SC_R_HDMI_PLL_1, 1, false, 0}, + + /* HDMI RX SS */ + { "hdmi-rx", IMX_SC_R_HDMI_RX, 1, false, 0}, + { "hdmi-rx-pwm", IMX_SC_R_HDMI_RX_PWM_0, 1, false, 0}, + { "hdmi-rx-i2c0", IMX_SC_R_HDMI_RX_I2C_0, 1, false, 0}, + { "hdmi-rx-bypass", IMX_SC_R_HDMI_RX_BYPASS, 1, false, 0}, + + /* SECURITY SS */ + { "sec-jr", IMX_SC_R_CAAM_JR2, 2, true, 2}, + + /* BOARD SS */ + { "board", IMX_SC_R_BOARD_R0, 8, true, 0}, }; static const struct imx_sc_pd_soc imx8qxp_scu_pd = {