From patchwork Fri Jul 21 05:46:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveenkumar I X-Patchwork-Id: 13321360 X-Patchwork-Delegate: daniel.lezcano@linaro.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D495EB64DD for ; Fri, 21 Jul 2023 05:47:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229898AbjGUFr0 (ORCPT ); Fri, 21 Jul 2023 01:47:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35504 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229899AbjGUFrP (ORCPT ); Fri, 21 Jul 2023 01:47:15 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C43A130C8; Thu, 20 Jul 2023 22:47:08 -0700 (PDT) Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36L4Qelh018223; Fri, 21 Jul 2023 05:47:01 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=71CbpnNRMkXI1Pos5VsiU4h+wLSJfDujY+eq0Ik/wD8=; b=hVg4wU7efxkDEb+8zVmJl8H7DYbtx/ocifTF+4Y6ObqjWaHgw99tlpwAfSxorvL3zN+o q/JdhJPeMaXw43XnsCJEbIYC4Vdw5LImpF5pAz3RI7lW5Iv02A4G63iWDLd2pom5q9zn 2VQ9u2ogz2q4r0l8nmkvdkx+vY9ofnQskSfYg2EzMPO7bVRmaNFxU2vQfDpGXzzLsQ0U gyOWXbmvkk5XqFLVcrcxtlmNfJQsAxw0uWJD9v9CYV4H2cE7kbnhApi6oUm2izRmc+9N uGiO0sFa4KCxVeIAQ/oEnCOeHvKYAGpNv3b2WUYlcm1gEeLqPUET8bwg5yAv5iYHE+XG Wg== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3ryfyf0e0h-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 21 Jul 2023 05:47:01 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 36L5l01m002574 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 21 Jul 2023 05:47:00 GMT Received: from hu-ipkumar-blr.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Thu, 20 Jul 2023 22:46:55 -0700 From: Praveenkumar I To: , , , , , , , , , , , , , , CC: Subject: [PATCH v5 3/5] arm64: dts: qcom: ipq5332: Add tsens node Date: Fri, 21 Jul 2023 11:16:17 +0530 Message-ID: <20230721054619.2366510-4-quic_ipkumar@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230721054619.2366510-1-quic_ipkumar@quicinc.com> References: <20230721054619.2366510-1-quic_ipkumar@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: p9NS27zZN4Vh3qK9yM8V0RPoBITRA3qh X-Proofpoint-ORIG-GUID: p9NS27zZN4Vh3qK9yM8V0RPoBITRA3qh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-21_02,2023-07-20_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=716 spamscore=0 mlxscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 adultscore=0 priorityscore=1501 impostorscore=0 clxscore=1015 malwarescore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307210052 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org IPQ5332 has tsens v2.3.3 peripheral. This patch adds the tsense node with nvmem cells for calibration data. Signed-off-by: Praveenkumar I --- [v5]: No changes. [v4]: No changes. [v3]: Reordered device nodes according to the address. [v2]: Included qfprom nodes only for available sensors and removed the offset suffix. arch/arm64/boot/dts/qcom/ipq5332.dtsi | 66 +++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index 8bfc2db44624..026f99fda00c 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -150,6 +150,46 @@ qfprom: efuse@a4000 { reg = <0x000a4000 0x721>; #address-cells = <1>; #size-cells = <1>; + + s11: s11@3a5 { + reg = <0x3a5 0x1>; + bits = <4 4>; + }; + + s12: s12@3a6 { + reg = <0x3a6 0x1>; + bits = <0 4>; + }; + + s13: s13@3a6 { + reg = <0x3a6 0x1>; + bits = <4 4>; + }; + + s14: s14@3ad { + reg = <0x3ad 0x2>; + bits = <7 4>; + }; + + s15: s15@3ae { + reg = <0x3ae 0x1>; + bits = <3 4>; + }; + + tsens_mode: mode@3e1 { + reg = <0x3e1 0x1>; + bits = <0 3>; + }; + + tsens_base0: base0@3e1 { + reg = <0x3e1 0x2>; + bits = <3 10>; + }; + + tsens_base1: base1@3e2 { + reg = <0x3e2 0x2>; + bits = <5 10>; + }; }; rng: rng@e3000 { @@ -159,6 +199,32 @@ rng: rng@e3000 { clock-names = "core"; }; + tsens: thermal-sensor@4a9000 { + compatible = "qcom,ipq5332-tsens"; + reg = <0x4a9000 0x1000>, + <0x4a8000 0x1000>; + nvmem-cells = <&tsens_mode>, + <&tsens_base0>, + <&tsens_base1>, + <&s11>, + <&s12>, + <&s13>, + <&s14>, + <&s15>; + nvmem-cell-names = "mode", + "base0", + "base1", + "s11", + "s12", + "s13", + "s14", + "s15"; + interrupts = ; + interrupt-names = "combined"; + #qcom,sensors = <5>; + #thermal-sensor-cells = <1>; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq5332-tlmm"; reg = <0x01000000 0x300000>;