From patchwork Wed Aug 9 17:39:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Apurva Nandan X-Patchwork-Id: 13348266 X-Patchwork-Delegate: daniel.lezcano@linaro.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02E87C04A94 for ; Wed, 9 Aug 2023 17:39:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232628AbjHIRjd (ORCPT ); Wed, 9 Aug 2023 13:39:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59422 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232505AbjHIRjc (ORCPT ); Wed, 9 Aug 2023 13:39:32 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A5D3310D2; Wed, 9 Aug 2023 10:39:31 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 379HdKLe058037; Wed, 9 Aug 2023 12:39:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691602760; bh=UIYntFequHuzIo6Glfr820/gXNIQMMks+9Ss5XA5YU0=; h=From:To:Subject:Date:In-Reply-To:References; b=ds87j5vfrjxggSFQ0JzvJbRiN5NljSaNC6fnIrKTe3VkfohVvsxESHDH769YrEcYU iKjOQ2apJhb5HXkCcQgBd1+U8UuZTh44lxFUdwrBVMwNBF3FiUrLT7vgG8VxeznDv5 YwoX82NrCGrdd5ASicKFZUeBEE47gUyWESHaYNT4= Received: from DFLE110.ent.ti.com (dfle110.ent.ti.com [10.64.6.31]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 379HdKHs082190 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 9 Aug 2023 12:39:20 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 9 Aug 2023 12:39:20 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 9 Aug 2023 12:39:20 -0500 Received: from TI.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 379Hd6gc077353; Wed, 9 Aug 2023 12:39:15 -0500 From: Apurva Nandan To: Apurva Nandan , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Rafael J Wysocki , Daniel Lezcano , Amit Kucheria , Zhang Rui , , , , , Udit Kumar , Keerthy J Subject: [PATCH 2/3] arm64: dts: ti: k3-j7200: Add the supported frequencies for A72 Date: Wed, 9 Aug 2023 23:09:04 +0530 Message-ID: <20230809173905.1844132-3-a-nandan@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230809173905.1844132-1-a-nandan@ti.com> References: <20230809173905.1844132-1-a-nandan@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Keerthy Add 750M, 1G, 1.5G & 2G as the supported frequencies for A72. This enables support for Dynamic Frequency Scaling(DFS) Signed-off-by: Keerthy Signed-off-by: Apurva Nandan --- arch/arm64/boot/dts/ti/k3-j7200.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi index ef73e6d7e858..7222c453096f 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi @@ -48,6 +48,10 @@ cpu0: cpu@0 { d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&L2_0>; + clocks = <&k3_clks 202 2>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ }; cpu1: cpu@1 { @@ -62,6 +66,30 @@ cpu1: cpu@1 { d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&L2_0>; + clocks = <&k3_clks 203 0>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + }; + }; + + cpu0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp4-2000000000 { + opp-hz = /bits/ 64 <2000000000>; + }; + + opp3-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + }; + + opp2-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + }; + + opp1-750000000 { + opp-hz = /bits/ 64 <750000000>; }; };