diff mbox series

[V2,6/7] Documentation: amd-pstate: introduce AMD Pstate Preferred Core

Message ID 20230815061546.3556083-7-li.meng@amd.com (mailing list archive)
State Changes Requested, archived
Headers show
Series AMD Pstate Preferred Core | expand

Commit Message

Meng, Li (Jassmine) Aug. 15, 2023, 6:15 a.m. UTC
Introduce AMD Pstate Preferred Core.

check preferred core state:
$ cat /sys/devices/system/cpu/amd-pstate/prefcore_state

Signed-off-by: Meng Li <li.meng@amd.com>
---
 Documentation/admin-guide/pm/amd-pstate.rst | 54 +++++++++++++++++++++
 1 file changed, 54 insertions(+)

Comments

Mario Limonciello Aug. 15, 2023, 3:34 p.m. UTC | #1
On 8/15/2023 01:15, Meng Li wrote:
> Introduce AMD Pstate Preferred Core.
> 
> check preferred core state:
> $ cat /sys/devices/system/cpu/amd-pstate/prefcore_state
> 
> Signed-off-by: Meng Li <li.meng@amd.com>
> ---
>   Documentation/admin-guide/pm/amd-pstate.rst | 54 +++++++++++++++++++++
>   1 file changed, 54 insertions(+)
> 
> diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst
> index 1cf40f69278c..ef2b69935311 100644
> --- a/Documentation/admin-guide/pm/amd-pstate.rst
> +++ b/Documentation/admin-guide/pm/amd-pstate.rst
> @@ -353,6 +353,48 @@ is activated.  In this mode, driver requests minimum and maximum performance
>   level and the platform autonomously selects a performance level in this range
>   and appropriate to the current workload.
>   
> +AMD Pstate Preferred Core
> +=================================
> +
> +The core frequency is subjected to the process variation in semiconductors.
> +Not all cores are able to reach the maximum frequency respecting the
> +infrastructure limits. Consequently, AMD has redefined the concept of
> +maximum frequency of a part. This means that a fraction of cores can reach
> +maximum frequency. To find the best process scheduling policy for a given
> +scenario, OS needs to know the core ordering informed by the platform through
> +highest performance capability register of the CPPC interface.
> +
> +``AMD Pstate Preferred Core`` enable the scheduler to favor scheduling on cores
> +can be get a higher frequency with lower voltage under preferred core.
> +And it has the ability to dynamically change the preferred core based on the
> +workload and platform conditions and accounting for thermals and aging.
> +
> +The priority metric will be initialized by the AMD Pstate driver. The AMD Pstate
> +driver will also determine whether or not ``AMD Pstate Preferred Core`` is
> +supported by the platform.
> +
> +AMD Pstate driver will provide an initial core ordering when the system boots.
> +The platform uses the CPPC interfaces to communicate the core ranking to the
> +operating system and scheduler to make sure that OS is choosing the cores
> +with highest performance firstly for scheduling the process. When AMD Pstate
> +driver receives a message with the highest performance change, it will
> +update the core ranking and set the cpu's priority.
> +
> +AMD Preferred Core Switch
> +=================================
> +Kernel Parameters
> +-----------------
> +
> +``AMD Pstate Preferred Core`` has two states: enable and disable.
> +Enable/disable states can be chosen by different kernel parameters.
> +Default enable ``AMD Pstate Preferred Core``.
> + > +``amd_prefcore=disable``
> +
> +If ``amd_prefcore=disable`` is passed to kernel command line option
> +then disable ``AMD Pstate Preferred Core`` if platform can support
> +the Preferred Core feature.
This all seems needlessly wordy.  Here's my suggestion.

"``AMD Pstate preferred core`` will be enabled if the underlying 
platform supports it.  It can be disabled by kernel parameter:

``amd_prefcore=disable``

> +
>   User Space Interface in ``sysfs`` - General
>   ===========================================
>   
> @@ -385,6 +427,18 @@ control its functionality at the system level.  They are located in the
>           to the operation mode represented by that string - or to be
>           unregistered in the "disable" case.
>   
> +``prefcore``
> +	Preferred Core state of the driver: "enabled" or "disabled".
> +
> +	"enabled"
> +		Enable the AMD Preferred Core.
> +
> +	"disabled"
> +		Disable the AMD Preferred Core
> +
> +
> +        This attribute is read-only to check the state of Preferred Core.
> +
>   ``cpupower`` tool support for ``amd-pstate``
>   ===============================================
>
diff mbox series

Patch

diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst
index 1cf40f69278c..ef2b69935311 100644
--- a/Documentation/admin-guide/pm/amd-pstate.rst
+++ b/Documentation/admin-guide/pm/amd-pstate.rst
@@ -353,6 +353,48 @@  is activated.  In this mode, driver requests minimum and maximum performance
 level and the platform autonomously selects a performance level in this range
 and appropriate to the current workload.
 
+AMD Pstate Preferred Core
+=================================
+
+The core frequency is subjected to the process variation in semiconductors.
+Not all cores are able to reach the maximum frequency respecting the
+infrastructure limits. Consequently, AMD has redefined the concept of
+maximum frequency of a part. This means that a fraction of cores can reach
+maximum frequency. To find the best process scheduling policy for a given
+scenario, OS needs to know the core ordering informed by the platform through
+highest performance capability register of the CPPC interface.
+
+``AMD Pstate Preferred Core`` enable the scheduler to favor scheduling on cores
+can be get a higher frequency with lower voltage under preferred core.
+And it has the ability to dynamically change the preferred core based on the
+workload and platform conditions and accounting for thermals and aging.
+
+The priority metric will be initialized by the AMD Pstate driver. The AMD Pstate
+driver will also determine whether or not ``AMD Pstate Preferred Core`` is
+supported by the platform.
+
+AMD Pstate driver will provide an initial core ordering when the system boots.
+The platform uses the CPPC interfaces to communicate the core ranking to the
+operating system and scheduler to make sure that OS is choosing the cores
+with highest performance firstly for scheduling the process. When AMD Pstate
+driver receives a message with the highest performance change, it will
+update the core ranking and set the cpu's priority.
+
+AMD Preferred Core Switch
+=================================
+Kernel Parameters
+-----------------
+
+``AMD Pstate Preferred Core`` has two states: enable and disable.
+Enable/disable states can be chosen by different kernel parameters.
+Default enable ``AMD Pstate Preferred Core``.
+
+``amd_prefcore=disable``
+
+If ``amd_prefcore=disable`` is passed to kernel command line option
+then disable ``AMD Pstate Preferred Core`` if platform can support
+the Preferred Core feature.
+
 User Space Interface in ``sysfs`` - General
 ===========================================
 
@@ -385,6 +427,18 @@  control its functionality at the system level.  They are located in the
         to the operation mode represented by that string - or to be
         unregistered in the "disable" case.
 
+``prefcore``
+	Preferred Core state of the driver: "enabled" or "disabled".
+
+	"enabled"
+		Enable the AMD Preferred Core.
+
+	"disabled"
+		Disable the AMD Preferred Core
+
+
+        This attribute is read-only to check the state of Preferred Core.
+
 ``cpupower`` tool support for ``amd-pstate``
 ===============================================