| Message ID | 20231001123853.200773-1-peng.fan@oss.nxp.com (mailing list archive) |
|---|---|
| State | Handled Elsewhere, archived |
| Headers | show |
| Series | pmdomain: imx: scu-pd: correct DMA2 channel | expand |
On Sun, 1 Oct 2023 at 14:34, Peng Fan (OSS) <peng.fan@oss.nxp.com> wrote: > > From: Peng Fan <peng.fan@nxp.com> > > Per "dt-bindings/firmware/imx/rsrc.h", `IMX_SC_R_DMA_2_CH0 + 5` not > equals to IMX_SC_R_DMA_2_CH5, so there should be two entries in > imx8qxp_scu_pd_ranges, otherwise the imx_scu_add_pm_domain may filter > out wrong power domains. > > Fixes: 927b7d15dcf2 ("genpd: imx: scu-pd: enlarge PD range") > Reported-by: Dong Aisheng <Aisheng.dong@nxp.com> > Signed-off-by: Peng Fan <peng.fan@nxp.com> Applied for fixes, thanks! Kind regards Uffe > --- > drivers/pmdomain/imx/scu-pd.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/pmdomain/imx/scu-pd.c b/drivers/pmdomain/imx/scu-pd.c > index 2f693b67ddb4..891c1d925a9d 100644 > --- a/drivers/pmdomain/imx/scu-pd.c > +++ b/drivers/pmdomain/imx/scu-pd.c > @@ -150,7 +150,8 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { > { "mclk-out-1", IMX_SC_R_MCLK_OUT_1, 1, false, 0 }, > { "dma0-ch", IMX_SC_R_DMA_0_CH0, 32, true, 0 }, > { "dma1-ch", IMX_SC_R_DMA_1_CH0, 16, true, 0 }, > - { "dma2-ch", IMX_SC_R_DMA_2_CH0, 32, true, 0 }, > + { "dma2-ch-0", IMX_SC_R_DMA_2_CH0, 5, true, 0 }, > + { "dma2-ch-1", IMX_SC_R_DMA_2_CH5, 27, true, 0 }, > { "dma3-ch", IMX_SC_R_DMA_3_CH0, 32, true, 0 }, > { "asrc0", IMX_SC_R_ASRC_0, 1, false, 0 }, > { "asrc1", IMX_SC_R_ASRC_1, 1, false, 0 }, > -- > 2.37.1 >
diff --git a/drivers/pmdomain/imx/scu-pd.c b/drivers/pmdomain/imx/scu-pd.c index 2f693b67ddb4..891c1d925a9d 100644 --- a/drivers/pmdomain/imx/scu-pd.c +++ b/drivers/pmdomain/imx/scu-pd.c @@ -150,7 +150,8 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { { "mclk-out-1", IMX_SC_R_MCLK_OUT_1, 1, false, 0 }, { "dma0-ch", IMX_SC_R_DMA_0_CH0, 32, true, 0 }, { "dma1-ch", IMX_SC_R_DMA_1_CH0, 16, true, 0 }, - { "dma2-ch", IMX_SC_R_DMA_2_CH0, 32, true, 0 }, + { "dma2-ch-0", IMX_SC_R_DMA_2_CH0, 5, true, 0 }, + { "dma2-ch-1", IMX_SC_R_DMA_2_CH5, 27, true, 0 }, { "dma3-ch", IMX_SC_R_DMA_3_CH0, 32, true, 0 }, { "asrc0", IMX_SC_R_ASRC_0, 1, false, 0 }, { "asrc1", IMX_SC_R_ASRC_1, 1, false, 0 },