| Message ID | 20240413152013.22307-6-quic_jkona@quicinc.com (mailing list archive) |
|---|---|
| State | Handled Elsewhere, archived |
| Headers | show |
| Series | PM: domains: Add control for switching back and forth to HW control | expand |
On 13/04/2024 16:20, Jagadeesh Kona wrote: > The Venus driver requires vcodec GDSC to be ON in SW mode for clock > operations and move it back to HW mode to gain power benefits. Earlier, > as there is no interface to switch the GDSC mode from GenPD framework, > the GDSC is moved to HW control mode as part of GDSC enable callback and > venus driver is writing to its POWER_CONTROL register to keep the GDSC ON > from SW whereever required. But the POWER_CONTROL register addresses > are not constant and can vary across the variants. > > Also as per the HW recommendation, the GDSC mode switching needs to be > controlled from respective GDSC register and this is a uniform approach > across all the targets. Hence use dev_pm_genpd_set_hwmode() API which > controls GDSC mode switching using its respective GDSC register. > > In venus V6 variants, the vcodec gdsc gets enabled in SW mode by default > with new HW_CTRL_TRIGGER flag and there is no need to switch it to SW > mode again after enable, hence add check to avoid switching gdsc to SW mode > again after gdsc enable. Similarly add check to avoid switching GDSC to HW > mode before disabling the GDSC, so GDSC gets enabled in SW mode in the next > enable. > > Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > --- When I tested this out on sm8250 a few months ago it was broken. I don't quite see in your commit logs, how the breakage was addressed. Can you provide some details ? --- bod
On 4/14/2024 6:09 PM, Bryan O'Donoghue wrote: > On 13/04/2024 16:20, Jagadeesh Kona wrote: >> The Venus driver requires vcodec GDSC to be ON in SW mode for clock >> operations and move it back to HW mode to gain power benefits. Earlier, >> as there is no interface to switch the GDSC mode from GenPD framework, >> the GDSC is moved to HW control mode as part of GDSC enable callback and >> venus driver is writing to its POWER_CONTROL register to keep the GDSC ON >> from SW whereever required. But the POWER_CONTROL register addresses >> are not constant and can vary across the variants. >> >> Also as per the HW recommendation, the GDSC mode switching needs to be >> controlled from respective GDSC register and this is a uniform approach >> across all the targets. Hence use dev_pm_genpd_set_hwmode() API which >> controls GDSC mode switching using its respective GDSC register. >> >> In venus V6 variants, the vcodec gdsc gets enabled in SW mode by default >> with new HW_CTRL_TRIGGER flag and there is no need to switch it to SW >> mode again after enable, hence add check to avoid switching gdsc to SW >> mode >> again after gdsc enable. Similarly add check to avoid switching GDSC >> to HW >> mode before disabling the GDSC, so GDSC gets enabled in SW mode in the >> next >> enable. >> >> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> >> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> >> --- > > When I tested this out on sm8250 a few months ago it was broken. > > I don't quite see in your commit logs, how the breakage was addressed. > > Can you provide some details ? > Thanks Bryan for your review! In earlier series, venus driver is switching the vcodec GDSC to HW control mode before disabling the GDSC by invoking vcodec_control_v4(..., false) in poweroff_coreid(). Due to this, the subsequent GDSC enable from venus driver is failing while polling for GDSC power ON status, since GDSC is under HW control mode and HW can keep the GDSC in disabled state. Now a check is added in poweroff_coreid() to avoid switching the GDSC to HW control mode before disabling the GDSC for Venus V6 variants that use this new API. Hence during the next GDSC enable, GDSC will be in SW mode and GDSC will powerup properly. Thanks, Jagadeesh > --- > bod >
On 14/04/2024 15:52, Jagadeesh Kona wrote: > > > On 4/14/2024 6:09 PM, Bryan O'Donoghue wrote: >> On 13/04/2024 16:20, Jagadeesh Kona wrote: >>> The Venus driver requires vcodec GDSC to be ON in SW mode for clock >>> operations and move it back to HW mode to gain power benefits. Earlier, >>> as there is no interface to switch the GDSC mode from GenPD framework, >>> the GDSC is moved to HW control mode as part of GDSC enable callback and >>> venus driver is writing to its POWER_CONTROL register to keep the >>> GDSC ON >>> from SW whereever required. But the POWER_CONTROL register addresses >>> are not constant and can vary across the variants. >>> >>> Also as per the HW recommendation, the GDSC mode switching needs to be >>> controlled from respective GDSC register and this is a uniform approach >>> across all the targets. Hence use dev_pm_genpd_set_hwmode() API which >>> controls GDSC mode switching using its respective GDSC register. >>> >>> In venus V6 variants, the vcodec gdsc gets enabled in SW mode by default >>> with new HW_CTRL_TRIGGER flag and there is no need to switch it to SW >>> mode again after enable, hence add check to avoid switching gdsc to >>> SW mode >>> again after gdsc enable. Similarly add check to avoid switching GDSC >>> to HW >>> mode before disabling the GDSC, so GDSC gets enabled in SW mode in >>> the next >>> enable. >>> >>> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> >>> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> >>> --- >> >> When I tested this out on sm8250 a few months ago it was broken. >> >> I don't quite see in your commit logs, how the breakage was addressed. >> >> Can you provide some details ? >> > > Thanks Bryan for your review! > > In earlier series, venus driver is switching the vcodec GDSC to HW > control mode before disabling the GDSC by invoking > vcodec_control_v4(..., false) in poweroff_coreid(). Due to this, the > subsequent GDSC enable from venus driver is failing while polling for > GDSC power ON status, since GDSC is under HW control mode and HW can > keep the GDSC in disabled state. > > Now a check is added in poweroff_coreid() to avoid switching the GDSC to > HW control mode before disabling the GDSC for Venus V6 variants that use > this new API. Hence during the next GDSC enable, GDSC will be in SW mode > and GDSC will powerup properly. Right so the intention is to have HW GDSC control during playback only - and then revert to SW control when no stream is active, right ? I tried your series on today's -next. Here is -next without your changes https://drive.google.com/file/d/1PFuLOlEp582rBQUvuwc9PNZUBxn1ioYf/view?usp=sharing and here is -next with your changes https://drive.google.com/file/d/1PHR4rZnWUH9Wp2B-itT5yCUXIMOMZrwM/view?usp=sharing The first time I tried that test the stopping/stuttering was worse. So yes the original crash was fixed but, this looks like a performance regression to me. Here's the tree I tested with. https://git.codelinaro.org/bryan.odonoghue/kernel/-/tree/linux-next-24-05-23-review?ref_type=heads --- bod
On 4/24/2024 5:46 AM, Bryan O'Donoghue wrote: > On 14/04/2024 15:52, Jagadeesh Kona wrote: >> >> >> On 4/14/2024 6:09 PM, Bryan O'Donoghue wrote: >>> On 13/04/2024 16:20, Jagadeesh Kona wrote: >>>> The Venus driver requires vcodec GDSC to be ON in SW mode for clock >>>> operations and move it back to HW mode to gain power benefits. Earlier, >>>> as there is no interface to switch the GDSC mode from GenPD framework, >>>> the GDSC is moved to HW control mode as part of GDSC enable callback >>>> and >>>> venus driver is writing to its POWER_CONTROL register to keep the >>>> GDSC ON >>>> from SW whereever required. But the POWER_CONTROL register addresses >>>> are not constant and can vary across the variants. >>>> >>>> Also as per the HW recommendation, the GDSC mode switching needs to be >>>> controlled from respective GDSC register and this is a uniform approach >>>> across all the targets. Hence use dev_pm_genpd_set_hwmode() API which >>>> controls GDSC mode switching using its respective GDSC register. >>>> >>>> In venus V6 variants, the vcodec gdsc gets enabled in SW mode by >>>> default >>>> with new HW_CTRL_TRIGGER flag and there is no need to switch it to SW >>>> mode again after enable, hence add check to avoid switching gdsc to >>>> SW mode >>>> again after gdsc enable. Similarly add check to avoid switching GDSC >>>> to HW >>>> mode before disabling the GDSC, so GDSC gets enabled in SW mode in >>>> the next >>>> enable. >>>> >>>> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> >>>> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> >>>> --- >>> >>> When I tested this out on sm8250 a few months ago it was broken. >>> >>> I don't quite see in your commit logs, how the breakage was addressed. >>> >>> Can you provide some details ? >>> >> >> Thanks Bryan for your review! >> >> In earlier series, venus driver is switching the vcodec GDSC to HW >> control mode before disabling the GDSC by invoking >> vcodec_control_v4(..., false) in poweroff_coreid(). Due to this, the >> subsequent GDSC enable from venus driver is failing while polling for >> GDSC power ON status, since GDSC is under HW control mode and HW can >> keep the GDSC in disabled state. >> >> Now a check is added in poweroff_coreid() to avoid switching the GDSC >> to HW control mode before disabling the GDSC for Venus V6 variants >> that use this new API. Hence during the next GDSC enable, GDSC will be >> in SW mode and GDSC will powerup properly. > > Right so the intention is to have HW GDSC control during playback only - > and then revert to SW control when no stream is active, right ? > > I tried your series on today's -next. > > Here is -next without your changes > > https://drive.google.com/file/d/1PFuLOlEp582rBQUvuwc9PNZUBxn1ioYf/view?usp=sharing > > and here is -next with your changes > > https://drive.google.com/file/d/1PHR4rZnWUH9Wp2B-itT5yCUXIMOMZrwM/view?usp=sharing > > The first time I tried that test the stopping/stuttering was worse. > > So yes the original crash was fixed but, this looks like a performance > regression to me. > Thanks Bryan for testing this series. Can you please confirm if this issue is observed in every run or only seen during the first run? Also please let me know on which platform this issue is observed? Thanks, Jagadeesh > Here's the tree I tested with. > > https://git.codelinaro.org/bryan.odonoghue/kernel/-/tree/linux-next-24-05-23-review?ref_type=heads > > --- > bod >
On 24/04/2024 10:45, Jagadeesh Kona wrote: > > Thanks Bryan for testing this series. Can you please confirm if this > issue is observed in every run or only seen during the first run? Also > please let me know on which platform this issue is observed? > > Thanks, > Jagadeesh rb5/sm8250 My observation was on a previous _boot_ the stuttering was worse. There is in the video capture three times that I count where the video halts briefly, I guess we need to vote or set an OPP so the firmware knows not to power-collapse quite so aggressively. --- bod
diff --git a/drivers/media/platform/qcom/venus/pm_helpers.c b/drivers/media/platform/qcom/venus/pm_helpers.c index 502822059498..4ce76ce6dd4d 100644 --- a/drivers/media/platform/qcom/venus/pm_helpers.c +++ b/drivers/media/platform/qcom/venus/pm_helpers.c @@ -412,10 +412,9 @@ static int vcodec_control_v4(struct venus_core *core, u32 coreid, bool enable) u32 val; int ret; - if (IS_V6(core)) { - ctrl = core->wrapper_base + WRAPPER_CORE_POWER_CONTROL_V6; - stat = core->wrapper_base + WRAPPER_CORE_POWER_STATUS_V6; - } else if (coreid == VIDC_CORE_ID_1) { + if (IS_V6(core)) + return dev_pm_genpd_set_hwmode(core->pmdomains->pd_devs[coreid], !enable); + else if (coreid == VIDC_CORE_ID_1) { ctrl = core->wrapper_base + WRAPPER_VCODEC0_MMCC_POWER_CONTROL; stat = core->wrapper_base + WRAPPER_VCODEC0_MMCC_POWER_STATUS; } else { @@ -451,9 +450,11 @@ static int poweroff_coreid(struct venus_core *core, unsigned int coreid_mask) vcodec_clks_disable(core, core->vcodec0_clks); - ret = vcodec_control_v4(core, VIDC_CORE_ID_1, false); - if (ret) - return ret; + if (!IS_V6(core)) { + ret = vcodec_control_v4(core, VIDC_CORE_ID_1, false); + if (ret) + return ret; + } ret = pm_runtime_put_sync(core->pmdomains->pd_devs[1]); if (ret < 0) @@ -467,9 +468,11 @@ static int poweroff_coreid(struct venus_core *core, unsigned int coreid_mask) vcodec_clks_disable(core, core->vcodec1_clks); - ret = vcodec_control_v4(core, VIDC_CORE_ID_2, false); - if (ret) - return ret; + if (!IS_V6(core)) { + ret = vcodec_control_v4(core, VIDC_CORE_ID_2, false); + if (ret) + return ret; + } ret = pm_runtime_put_sync(core->pmdomains->pd_devs[2]); if (ret < 0) @@ -488,9 +491,11 @@ static int poweron_coreid(struct venus_core *core, unsigned int coreid_mask) if (ret < 0) return ret; - ret = vcodec_control_v4(core, VIDC_CORE_ID_1, true); - if (ret) - return ret; + if (!IS_V6(core)) { + ret = vcodec_control_v4(core, VIDC_CORE_ID_1, true); + if (ret) + return ret; + } ret = vcodec_clks_enable(core, core->vcodec0_clks); if (ret) @@ -506,9 +511,11 @@ static int poweron_coreid(struct venus_core *core, unsigned int coreid_mask) if (ret < 0) return ret; - ret = vcodec_control_v4(core, VIDC_CORE_ID_2, true); - if (ret) - return ret; + if (!IS_V6(core)) { + ret = vcodec_control_v4(core, VIDC_CORE_ID_2, true); + if (ret) + return ret; + } ret = vcodec_clks_enable(core, core->vcodec1_clks); if (ret)