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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS3PEPF0000C37C.mail.protection.outlook.com (10.167.23.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7544.18 via Frontend Transport; Tue, 7 May 2024 17:48:38 +0000 Received: from AUS-P9-MLIMONCI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 7 May 2024 12:48:37 -0500 From: Mario Limonciello To: CC: , , , , Perry Yuan , Mario Limonciello Subject: [PATCH] cpufreq: amd-pstate: fix the highest frequency issue which limit performance Date: Tue, 7 May 2024 12:48:10 -0500 Message-ID: <20240507174810.46709-1-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C37C:EE_|LV2PR12MB5821:EE_ X-MS-Office365-Filtering-Correlation-Id: 8b4c1114-42d4-4877-3a1a-08dc6ebded1f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|1800799015|376005|82310400017|36860700004; X-Microsoft-Antispam-Message-Info: Wc7Wf2AmPYwtuwsRuWNC2T21qZJAKiceByUQIoTY3NB/GU6PJMYNtGF87N7Q8Xn7SF0aLFcJBmeXocK1VaJZWPrwY+tpkRYFkhguDDKsYfTIA/Jx7xuWf2ectCMwAgShqCsCUBYsjE7kxvTq2l3iE/bXYOZA2bretMZLoHiv68xWQnD1+ztlWSyYQoYhtw/X9vO4aHeEmB4PxgT/kpAKe77sylMUkjI+AmuJ24akkSzjTmwOfZ4Mhx/vNTdShvQKLtekQelXTQ8EAMp+S5HxScggEVYuK8VgwT0SmartS4BGLI29aDsKZBOAM+pShoq29ELZsLL0PlnaM2J3doJAUtLoobFJvDUD44WwGWuMDk+TJEIrjANMN6PlN20JCoX+xItlXd8rEAFU8Zf8lwguM7DvJ7g/5UIWS83i7o+Fb6PzlstVf2Km+cWiHNrwiRtO9gtthJI/2ND1phH+qFo/AB3I8jSYQYRkscWtid07lIFtguG0ZHWHEUJtgNiJ1nZOkNbgTQCBUiD5x32G6NWTWsR3a9ePnzsHWYWwsJf7MAlM3YwnTQyzr8gcmC0QV0vawofmsx2UEGrtWalIufKN2O3CZaTUlgcrMMQIjoGKXl2AH1Ut+dJJp0ll2ujs2wCF+xps0rdqhPnJviKLqcW9QkK+ZfvBmiqfJG5BwRwtaal5bMxFFlxAGJij1ngy2xD/Dgr2yR6X5f3lTtlp0Z796WeqHTDYkRLoDD/I8hoNcbOuXqhV9zs2z1oMiJPnLS5a7TIqJhMLWgXpI6iEga6J+O5fL2E7EKXK3Er6h1zNbAebc6aug97cQRwOtEzTzkOlDrVuVekXgdqZeUQIPVaadzhFQJz5hgLqOnvXElAYLJPUMIVGdtTLnPJrKFXH9XMkycl74zclNPgcQdUXfw+fD77l1YuOR4TENNjVXS5ts7u8Sfhz9MwV0+G1wwGXFYDmdWkwj1iLk095N0RAGkw7rB1/2fys62UUKyrT7HmV1JBuU3U3rn6/vcfPtDJzMx4iPTJMvs3WfrkztKC5q6/YufLfHdx+Nat025FcmSmYJlhjMC6I/dQDEE73twqeuDuNJ6wlhJxJBd1RqGqVb0/kKP+nNwh8qnCp/O/QEaxAcEDkHur4tra7RdCqDDWfI641PB/JF8Gl0dNn6u58c3Sc1Pg6mPPGJNXYvEeBGbtRD1144k/NsvMbYm02adIZbL78weXvBaYEtOmeDqxpdDyyDrUzen9z69je5MouNZxpBupY5gdrOWO2SyZjrxqyCvp2z3w6q9PM6TOMeb4ze1tsNDmIyZn0krmCGbctELHAHJyKlvxFGiEQ4AppNoK3nTKzbp62jkIQMIdBDp4jXSn3mA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(1800799015)(376005)(82310400017)(36860700004);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 May 2024 17:48:38.4951 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8b4c1114-42d4-4877-3a1a-08dc6ebded1f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C37C.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5821 From: Perry Yuan To address the performance drop issue, an optimization has been implemented. The incorrect highest performance value previously set by the low-level power firmware for AMD CPUs with Family ID 0x19 and Model ID ranging from 0x70 to 0x7F series has been identified as the cause. To resolve this, a check has been implemented to accurately determine the CPU family and model ID. The correct highest performance value is now set and the performance drop caused by the incorrect highest performance value are eliminated. Before the fix, the highest frequency was set to 4200MHz, now it is set to 4971MHz which is correct. CPU NODE SOCKET CORE L1d:L1i:L2:L3 ONLINE MAXMHZ MINMHZ MHZ 0 0 0 0 0:0:0:0 yes 4971.0000 400.0000 400.0000 1 0 0 0 0:0:0:0 yes 4971.0000 400.0000 400.0000 2 0 0 1 1:1:1:0 yes 4971.0000 400.0000 4865.8140 3 0 0 1 1:1:1:0 yes 4971.0000 400.0000 400.0000 Fixes: f3a052391822 ("cpufreq: amd-pstate: Enable amd-pstate preferred core support") Closes: https://bugzilla.kernel.org/show_bug.cgi?id=218759 Signed-off-by: Perry Yuan Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello Tested-by: Gaha Bana --- This comes from patch 10 originally by Perry in [1]. As there is a regression in 6.9 it's pulled out separately from the rest of the series. This should go to 6.9 final if possible; otherwise 6.10-rc1 and CC to stable at that time. [1] https://lore.kernel.org/linux-pm/cover.1715065568.git.perry.yuan@amd.com/T/#t. drivers/cpufreq/amd-pstate.c | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index fbe57d356ee4..4859902eaf1a 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -50,7 +50,8 @@ #define AMD_PSTATE_TRANSITION_LATENCY 20000 #define AMD_PSTATE_TRANSITION_DELAY 1000 -#define AMD_PSTATE_PREFCORE_THRESHOLD 166 +#define CPPC_HIGHEST_PERF_PERFORMANCE 196 +#define CPPC_HIGHEST_PERF_DEFAULT 166 /* * TODO: We need more time to fine tune processors with shared memory solution @@ -264,6 +265,21 @@ static inline int amd_pstate_enable(bool enable) return static_call(amd_pstate_enable)(enable); } +static u32 amd_pstate_highest_perf_set(struct amd_cpudata *cpudata) +{ + struct cpuinfo_x86 *c = &cpu_data(0); + + /* + * For AMD CPUs with Family ID 19H and Model ID range 0x70 to 0x7f, + * the highest performance level is set to 196. + * https://bugzilla.kernel.org/show_bug.cgi?id=218759 + */ + if (c->x86 == 0x19 && (c->x86_model >= 0x70 && c->x86_model <= 0x7f)) + return CPPC_HIGHEST_PERF_PERFORMANCE; + + return CPPC_HIGHEST_PERF_DEFAULT; +} + static int pstate_init_perf(struct amd_cpudata *cpudata) { u64 cap1; @@ -280,7 +296,7 @@ static int pstate_init_perf(struct amd_cpudata *cpudata) * the default max perf. */ if (cpudata->hw_prefcore) - highest_perf = AMD_PSTATE_PREFCORE_THRESHOLD; + highest_perf = amd_pstate_highest_perf_set(cpudata); else highest_perf = AMD_CPPC_HIGHEST_PERF(cap1); @@ -304,7 +320,7 @@ static int cppc_init_perf(struct amd_cpudata *cpudata) return ret; if (cpudata->hw_prefcore) - highest_perf = AMD_PSTATE_PREFCORE_THRESHOLD; + highest_perf = amd_pstate_highest_perf_set(cpudata); else highest_perf = cppc_perf.highest_perf;