From patchwork Wed May 8 13:47:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ilpo_J=C3=A4rvinen?= X-Patchwork-Id: 13658819 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED2676F08B; Wed, 8 May 2024 13:48:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715176102; cv=none; b=oUwz4bGROnG9YcJkbkXWumgvMNltD17JeNrxKKPWES52CZD8bNZXYXy6VGCfAct4JpAHDk/UiqHpX9hZpQzbZYIql1j27Bw/iJam+m1+mtMfPOfyR5pvaw0BXNI0aQ7RF7uMQn8kPkbYO1eUZ8iv7YjFPaUvXgVZSmKNHSvXC8A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715176102; c=relaxed/simple; bh=C+sgypmpkReKGmyko3Nfq67Es9ksH8VsgZ2bo7aqLj4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=Rsn5+A+T8ed8YB80GNb3vCWI9tTYzXljPk7JpBYLZ/NA1DWpvwjf3VQy4iz0NEEx5gcZIAXWe+Wie8UF+nAuk2Z+cNGTbLO+tgHAWrpR8CZLcGVZ4RDFGmEbR8GiohHTGkq/mlEKiKd4C007ugIQUFQxW6TY0Ae7YlAfMacnzzE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=UU3VJf+U; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="UU3VJf+U" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1715176101; x=1746712101; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=C+sgypmpkReKGmyko3Nfq67Es9ksH8VsgZ2bo7aqLj4=; b=UU3VJf+U/nSvpFzwjQxLoqom7o/yaFKusPwHOghXN3VdXtNT7H4lGzl+ x3EDSU26zasC+I/9DCJYFXlXiLfNjGU/wKo+ovTGVuWaLEpqpqcXfejnu ry5s5qsyMoWmXtfXI1EyZayYHckQ6MjjJk6EYQNCAFJwpCLAs0dyFkHl2 LQDeEc/N7Gnw8i9D/sQ/TY4bhXdXC486V8shNYP/ZC/punQ7ZKgcPQ5Wm oIcpiWyuvObGKsegAfxLXRyOlbW1lM9/cLWEP2Of4rCO8DlVJDSWcdOwk G8jRyUBaOZjUe3uClaiJ13Cu0dEwDOXNzPnIr/tD2HU7117ihOLGOu1P8 g==; X-CSE-ConnectionGUID: Hm2z6y3KRRyixNY0dzUi4g== X-CSE-MsgGUID: 4h+rIjNtSpmd/fnWPP+Rjg== X-IronPort-AV: E=McAfee;i="6600,9927,11066"; a="10906404" X-IronPort-AV: E=Sophos;i="6.08,145,1712646000"; d="scan'208";a="10906404" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2024 06:48:20 -0700 X-CSE-ConnectionGUID: UgV5ODWLS0GoOx4Ys9xqAA== X-CSE-MsgGUID: 9T98cWoHS5qNPqS/DUxdjA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,145,1712646000"; d="scan'208";a="28855160" Received: from ijarvine-desk1.ger.corp.intel.com (HELO localhost) ([10.245.247.80]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2024 06:48:14 -0700 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Lukas Wunner , Alexandru Gagniuc , Krishna chaitanya chundru , Srinivas Pandruvada , "Rafael J. Wysocki" , linux-pm@vger.kernel.org, Jonathan Corbet , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Daniel Lezcano , Amit Kucheria , Zhang Rui , Christophe JAILLET , =?utf-8?q?Ilpo_J=C3=A4r?= =?utf-8?q?vinen?= Subject: [PATCH v5 1/8] PCI: Protect Link Control 2 Register with RMW locking Date: Wed, 8 May 2024 16:47:37 +0300 Message-Id: <20240508134744.52134-2-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240508134744.52134-1-ilpo.jarvinen@linux.intel.com> References: <20240508134744.52134-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 PCIe Bandwidth Controller performs RMW accesses the Link Control 2 Register which can occur concurrently to other sources of Link Control 2 Register writes. Therefore, add Link Control 2 Register among the PCI Express Capability Registers that need RMW locking. Signed-off-by: Ilpo Järvinen Reviewed-by: Lukas Wunner --- Documentation/PCI/pciebus-howto.rst | 14 +++++++++----- include/linux/pci.h | 1 + 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/Documentation/PCI/pciebus-howto.rst b/Documentation/PCI/pciebus-howto.rst index a0027e8fb0d0..cd7857dd37aa 100644 --- a/Documentation/PCI/pciebus-howto.rst +++ b/Documentation/PCI/pciebus-howto.rst @@ -217,8 +217,12 @@ capability structure except the PCI Express capability structure, that is shared between many drivers including the service drivers. RMW Capability accessors (pcie_capability_clear_and_set_word(), pcie_capability_set_word(), and pcie_capability_clear_word()) protect -a selected set of PCI Express Capability Registers (Link Control -Register and Root Control Register). Any change to those registers -should be performed using RMW accessors to avoid problems due to -concurrent updates. For the up-to-date list of protected registers, -see pcie_capability_clear_and_set_word(). +a selected set of PCI Express Capability Registers: + +* Link Control Register +* Root Control Register +* Link Control 2 Register + +Any change to those registers should be performed using RMW accessors to +avoid problems due to concurrent updates. For the up-to-date list of +protected registers, see pcie_capability_clear_and_set_word(). diff --git a/include/linux/pci.h b/include/linux/pci.h index 16493426a04f..93faaf08965e 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1273,6 +1273,7 @@ static inline int pcie_capability_clear_and_set_word(struct pci_dev *dev, { switch (pos) { case PCI_EXP_LNKCTL: + case PCI_EXP_LNKCTL2: case PCI_EXP_RTCTL: return pcie_capability_clear_and_set_word_locked(dev, pos, clear, set);