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Shenoy" , "Mario Limonciello" , Perry Yuan , , , , , "Shyam Sundar S K" Subject: [PATCH v2 10/13] x86/cpu: Enable SD_ASYM_PACKING for DIE Domain on AMD Processors Date: Thu, 10 Oct 2024 14:37:02 -0500 Message-ID: <20241010193705.10362-11-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241010193705.10362-1-mario.limonciello@amd.com> References: <20241010193705.10362-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015CA:EE_|CY8PR12MB7413:EE_ X-MS-Office365-Filtering-Correlation-Id: 3aff80c1-5765-407f-a541-08dce96306c4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: y6Q3fReQxGnsgimihTNYp/nH+hMgGz4wVVIOamIxwK1sDF8pwuzXCtdujcrlIfeBkPrwlQTtkGIwyQ8fyos0pOJMB4Gp/TlPrg8wCOCR0eoIGGIKCj+YJlbOpmD8YKquP8f/6eW8PDS//zLiG67N2oZ5w2037vHkKUaZdmlEoN9ePCZuPIRc5ANW60iRw0r8xqhAjhgUQDrOqUm0zqttadPCVkDLHliRyA+TrBgbmT8Hi4JnSYHcTU5vtDWrAStcKlCjfL1N6vfo4KjMDgcHy7nBjmcgGRAhq4+MZY9Fb1jkp8/7NSTye0G+sg1kgzaXWfIBFOBnb1O+ZSSMaCCiLaVrvsQe7Y8Na8qUeqihBRui2QehdyiAT8tZUsOJktJw1Vw775rnUN3+3UXh4tpQPLruF95GSX3RplFVg9fguE+0tsekidzt7ruYyCFG5PtrZZhUBO100nj8+R31Qze9QqwbXpDsJT+Lx+dUkWODhI5LQHZHKmMzHMSSyIBQplz5lHB2GYp0Lv8Gqryf6iV85KObhq0m0ht6TkZ0A45NWuhrFHGiqABvDNC2j8qMgFnh80jsbRX3+GuiFPhoGwV4T2Gd88c2k6ngVexgoxO2bboDzPVoo/sbPEG3sCN+McHGDOx0PCDOeZe51gqsVR/jttbtyZ67qz6op+Xw+R2RihXelIuqd92PvHNJfFhweGGv/VaIbRmHKGdINqRLc9XHrh5/QqdCz3lY9EIQm+FHmkvEOyOYBmJrimGGFXJxVSmapiCOvly3WuZpInveaSqyXL/d4BEri8j9VVNS/J2mZ8giMZLvOotugFxE7KrxQEQOflFFYlTrUlG0FTt0T++qWQwpnksr74HjqGaQLfb1uOSOjjEYkV5KNxt7rUsH8adcmlaFpmBAZnI/EJa1+ORW4SYqVPVvYtloajfCBIEFRoCdbl8+7W1wPkaq3RDcwBOEQdggg8KkschV0NpSZmlm1BaFbjiwdncLS7Tqp+wQcdu6NoIGKSTo4sfBdXjS5+Vz0TdpjYDw48lnxeJY1bxbfct73ZFe0jjpj8XauNfuBkZHr+EGllFZjvRFo8ym3WzMjBOA1qNGHkQps3Qfv4r2xxpeXPxIt+tW41F78GRbaLCyBhYFq0foZek7tMVQy6fJ8LeK2UmdsOnZGznrqW7qFC+4PYFoAD3oa5clvhNL0qszzzkVHncasCjk0ZabeQfk8H13t8KLzAMz/tQxezvQtdu/AsUYe05PbsY2WiJ/BKIw45M/uYlbM8wgGhITi/bbej/bSne8nXobd31l+hHnInG/T3XvzwmImDATVxseSCjSrQMIoixiAkSQjqZ2U8pXNT2WDyL8UeRjycbRHt6FTE5sUCsNmC1/wUKbNk2bCWjgOXFB2AOeiS4QsZCfbW2M X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(376014)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2024 19:37:50.3571 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3aff80c1-5765-407f-a541-08dce96306c4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015CA.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7413 From: Perry Yuan Enable the SD_ASYM_PACKING domain flag for the DIE domain on AMD heterogeneous processors. This flag is beneficial for processors with one or more CCDs and relies on x86_sched_itmt_flags(). Signed-off-by: Perry Yuan Signed-off-by: Mario Limonciello --- v2: * Whitespace --- arch/x86/kernel/smpboot.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index 766f092dab80..c01bb75d0375 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -497,8 +497,9 @@ static int x86_cluster_flags(void) static int x86_die_flags(void) { - if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) - return x86_sched_itmt_flags(); + if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU) || + cpu_feature_enabled(X86_FEATURE_HETERO_CORE_TOPOLOGY)) + return x86_sched_itmt_flags(); return 0; }