From patchwork Thu Oct 24 17:05:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cody Eksal X-Patchwork-Id: 13849504 Received: from thales.epochal.quest (thales.epochal.quest [51.222.15.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 518DD1FBF45; Thu, 24 Oct 2024 17:19:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=51.222.15.28 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729790356; cv=none; b=Z9caYtR2dCpjh7ZWYp60FzWovTTgrCJaG1+/FGITf2kG8pHPXTMBVsP3Z9a8akzhswp4t3nDyuLfF+oB17S8Y0sgpoRdcQSrVZsRi8bjj08+XJ/FfoGCMq1h1ZiphG65CLZql3Sz0HHu4XpJTztU3zLeJL/O3MZ2xkYPGr89BVU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729790356; c=relaxed/simple; bh=8tBNvio1ObQTdhVztprL74DuHbZpuJ/042vXRGsdyBc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=OuGPNiQpnsgoGkBV1mZHcHIXsdtXIWRGbnK1E2hJdRdq3azw63Wx1uNPLKL43wqBepJV8oem3s/YxGhEB9nlRBRkce0b1d7g7n8xrtr+P4b1YhBZ27Gmxj1nKChtmDDISHz4FC3P1KUJoLqYs984qwk8gQcoKH//I0IVI7lflE0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=epochal.quest; spf=pass smtp.mailfrom=epochal.quest; dkim=pass (2048-bit key) header.d=epochal.quest header.i=@epochal.quest header.b=gBpbT0s4; arc=none smtp.client-ip=51.222.15.28 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=epochal.quest Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=epochal.quest Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=epochal.quest header.i=@epochal.quest header.b="gBpbT0s4" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=epochal.quest; s=default; t=1729789781; bh=8tBNvio1ObQTdhVztprL74DuHbZpuJ/042vXRGsdyBc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gBpbT0s4l/mH/5QaMbAWMR9X/xoQ2LxH8ZCno0hvGjlhDc0U6Qp28p8TrQ6cLjCPt 2JdrefvdU6KCkLy0g7yzngC/ECTV18sfnhi3F5dLI1qoil3nT/rXYzu6aIJ0m35q3+ AZPfQdcVTq7ZeKK3gTHKbBSADrQmFoeehWhsb2RAq5BsjuYcjo/y6IoeXVA7Ju+Sjj /fsawnI5GeVxUwBixvNrppUX7BK9mfaazcRMhwOpdzWKiJOuwwOhl6nZ0EcFdg1tnV NjeqgtTgIUhtvTq6HJFNZZorHxqe/mvKk3VX9e7GPPODi/qhKTlDzs8N61/d88LNSy vuLAAireR7sXg== X-Virus-Scanned: by epochal.quest From: Cody Eksal To: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-usb@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Cody Eksal , Andre Przywara , Parthiban , Yangtao Li , Florian Fainelli , Vinod Koul , Linus Walleij , Thierry Reding , Krzysztof Kozlowski , Maxime Ripard , Greg Kroah-Hartman , Yangtao Li , Viresh Kumar , Nishanth Menon , Stephen Boyd , Kishon Vijay Abraham I , "Rafael J. Wysocki" Subject: [PATCH 01/13] arm64: dts: allwinner: A100: Add PMU mode Date: Thu, 24 Oct 2024 14:05:19 -0300 Message-ID: <20241024170540.2721307-2-masterr3c0rd@epochal.quest> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241024170540.2721307-1-masterr3c0rd@epochal.quest> References: <20241024170540.2721307-1-masterr3c0rd@epochal.quest> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Yangtao Li Add the Performance Monitoring Unit (PMU) device tree node to the A100 .dtsi, which tells DT users which interrupts are triggered by PMU overflow events on each core. Signed-off-by: Yangtao Li Reviewed-by: Andre Przywara Signed-off-by: Cody Eksal --- arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi index a3dccf193765..1eca7c220ede 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi @@ -25,21 +25,21 @@ cpu0: cpu@0 { enable-method = "psci"; }; - cpu@1 { + cpu1: cpu@1 { compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x1>; enable-method = "psci"; }; - cpu@2 { + cpu2: cpu@2 { compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x2>; enable-method = "psci"; }; - cpu@3 { + cpu3: cpu@3 { compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x3>; @@ -47,6 +47,15 @@ cpu@3 { }; }; + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + psci { compatible = "arm,psci-1.0"; method = "smc";