| Message ID | 20241119-topic-sm8x50-gpu-bw-vote-v2-3-4deb87be2498@linaro.org (mailing list archive) |
|---|---|
| State | Handled Elsewhere, archived |
| Headers | show |
| Series | drm/msm: adreno: add support for DDR bandwidth scaling via GMU | expand |
On Tue, Nov 19, 2024 at 06:56:38PM +0100, Neil Armstrong wrote: > Now the features defines have the right name, introduce a features > bitfield and move the features defines in it, fixing all code checking > for them. > > No functional changes intended. I think it might be better to squahs this patch into the previous one, it would simplify checking that we use .quirks for ADRENO_QUIRK_foo and .features for ADRENO_FEAT_bar. > > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > --- > drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 34 +++++++++++++++--------------- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4 ++-- > drivers/gpu/drm/msm/adreno/adreno_device.c | 2 +- > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 7 +++--- > 4 files changed, 24 insertions(+), 23 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > index 825c820def315968d508973c8ae40c7c7b646569..93f0d4bf50ba773ecde93e6c29a2fcec24ebb7b3 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > @@ -743,7 +743,7 @@ static const struct adreno_info a6xx_gpus[] = { > }, > .gmem = SZ_512K, > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT, > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT, > .init = a6xx_gpu_init, > .zapfw = "a615_zap.mbn", > .a6xx = &(const struct a6xx_info) { > @@ -769,7 +769,7 @@ static const struct adreno_info a6xx_gpus[] = { > }, > .gmem = SZ_512K, > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT, > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT, > .init = a6xx_gpu_init, > .a6xx = &(const struct a6xx_info) { > .protect = &a630_protect, > @@ -839,7 +839,7 @@ static const struct adreno_info a6xx_gpus[] = { > }, > .gmem = SZ_512K, > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT, > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT, > .init = a6xx_gpu_init, > .zapfw = "a615_zap.mdt", > .a6xx = &(const struct a6xx_info) { > @@ -864,7 +864,7 @@ static const struct adreno_info a6xx_gpus[] = { > }, > .gmem = SZ_512K, > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | > ADRENO_FEAT_HAS_HW_APRIV, > .init = a6xx_gpu_init, > .zapfw = "a620_zap.mbn", > @@ -892,7 +892,7 @@ static const struct adreno_info a6xx_gpus[] = { > }, > .gmem = SZ_1M, > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT, > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT, > .init = a6xx_gpu_init, > .zapfw = "a630_zap.mdt", > .a6xx = &(const struct a6xx_info) { > @@ -911,7 +911,7 @@ static const struct adreno_info a6xx_gpus[] = { > }, > .gmem = SZ_1M, > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT, > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT, > .init = a6xx_gpu_init, > .zapfw = "a640_zap.mdt", > .a6xx = &(const struct a6xx_info) { > @@ -934,7 +934,7 @@ static const struct adreno_info a6xx_gpus[] = { > }, > .gmem = SZ_1M + SZ_128K, > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | > ADRENO_FEAT_HAS_HW_APRIV, > .init = a6xx_gpu_init, > .zapfw = "a650_zap.mdt", > @@ -961,7 +961,7 @@ static const struct adreno_info a6xx_gpus[] = { > }, > .gmem = SZ_1M + SZ_512K, > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | > ADRENO_FEAT_HAS_HW_APRIV, > .init = a6xx_gpu_init, > .zapfw = "a660_zap.mdt", > @@ -981,7 +981,7 @@ static const struct adreno_info a6xx_gpus[] = { > }, > .gmem = SZ_1M + SZ_512K, > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | > ADRENO_FEAT_HAS_HW_APRIV, > .init = a6xx_gpu_init, > .a6xx = &(const struct a6xx_info) { > @@ -1000,7 +1000,7 @@ static const struct adreno_info a6xx_gpus[] = { > }, > .gmem = SZ_512K, > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | > ADRENO_FEAT_HAS_HW_APRIV, > .init = a6xx_gpu_init, > .zapfw = "a660_zap.mbn", > @@ -1028,7 +1028,7 @@ static const struct adreno_info a6xx_gpus[] = { > }, > .gmem = SZ_2M, > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT, > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT, > .init = a6xx_gpu_init, > .zapfw = "a640_zap.mdt", > .a6xx = &(const struct a6xx_info) { > @@ -1046,7 +1046,7 @@ static const struct adreno_info a6xx_gpus[] = { > }, > .gmem = SZ_4M, > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | > ADRENO_FEAT_HAS_HW_APRIV, > .init = a6xx_gpu_init, > .zapfw = "a690_zap.mdt", > @@ -1331,7 +1331,7 @@ static const struct adreno_info a7xx_gpus[] = { > }, > .gmem = SZ_128K, > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > - .quirks = ADRENO_FEAT_HAS_HW_APRIV, > + .features = ADRENO_FEAT_HAS_HW_APRIV, > .init = a6xx_gpu_init, > .zapfw = "a702_zap.mbn", > .a6xx = &(const struct a6xx_info) { > @@ -1355,7 +1355,7 @@ static const struct adreno_info a7xx_gpus[] = { > }, > .gmem = SZ_2M, > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | > ADRENO_FEAT_HAS_HW_APRIV | > ADRENO_FEAT_PREEMPTION, > .init = a6xx_gpu_init, > @@ -1377,7 +1377,7 @@ static const struct adreno_info a7xx_gpus[] = { > }, > .gmem = 3 * SZ_1M, > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | > ADRENO_FEAT_HAS_HW_APRIV | > ADRENO_FEAT_PREEMPTION, > .init = a6xx_gpu_init, > @@ -1400,7 +1400,7 @@ static const struct adreno_info a7xx_gpus[] = { > }, > .gmem = 3 * SZ_1M, > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | > ADRENO_FEAT_HAS_HW_APRIV | > ADRENO_FEAT_PREEMPTION, > .init = a6xx_gpu_init, > @@ -1422,7 +1422,7 @@ static const struct adreno_info a7xx_gpus[] = { > }, > .gmem = 3 * SZ_1M, > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | > ADRENO_FEAT_HAS_HW_APRIV | > ADRENO_FEAT_PREEMPTION, > .init = a6xx_gpu_init, > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > index 2ebd3fac212576a1507e0b6afe2560cd0408dd89..654d0cff421f15901cd4bf33b41e70004634ec75 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -2478,7 +2478,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) > adreno_gpu->gmu_is_wrapper = of_device_is_compatible(node, "qcom,adreno-gmu-wrapper"); > > adreno_gpu->base.hw_apriv = > - !!(config->info->quirks & ADRENO_FEAT_HAS_HW_APRIV); > + !!(config->info->features & ADRENO_FEAT_HAS_HW_APRIV); > > /* gpu->info only gets assigned in adreno_gpu_init() */ > is_a7xx = config->info->family == ADRENO_7XX_GEN1 || > @@ -2495,7 +2495,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) > } > > if ((enable_preemption == 1) || (enable_preemption == -1 && > - (config->info->quirks & ADRENO_FEAT_PREEMPTION))) > + (config->info->features & ADRENO_FEAT_PREEMPTION))) > ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 4); > else if (is_a7xx) > ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 1); > diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c > index 09d4569f77528c2a20cabc814668c4c930dd07f1..11a228472fa0cef3b6e4e21a366470fbbc3ea8df 100644 > --- a/drivers/gpu/drm/msm/adreno/adreno_device.c > +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c > @@ -207,7 +207,7 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) > > priv->is_a2xx = info->family < ADRENO_3XX; > priv->has_cached_coherent = > - !!(info->quirks & ADRENO_FEAT_HAS_CACHED_COHERENT); > + !!(info->features & ADRENO_FEAT_HAS_CACHED_COHERENT); > > gpu = info->init(drm); > if (IS_ERR(gpu)) { > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > index 8782c25e8a393ec7d9dc23ad450908d039bd08c5..4702d4cfca3b58fb3cbb25cb6805f1c19be2ebcb 100644 > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > @@ -55,9 +55,9 @@ enum adreno_family { > #define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1) > #define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2) > > -#define ADRENO_FEAT_HAS_HW_APRIV BIT(3) > -#define ADRENO_FEAT_HAS_CACHED_COHERENT BIT(4) > -#define ADRENO_FEAT_PREEMPTION BIT(5) > +#define ADRENO_FEAT_HAS_HW_APRIV BIT(0) > +#define ADRENO_FEAT_HAS_CACHED_COHERENT BIT(1) > +#define ADRENO_FEAT_PREEMPTION BIT(2) > > /* Helper for formating the chip_id in the way that userspace tools like > * crashdec expect. > @@ -98,6 +98,7 @@ struct adreno_info { > uint32_t revn; > const char *fw[ADRENO_FW_MAX]; > uint32_t gmem; > + u64 features; > u64 quirks; > struct msm_gpu *(*init)(struct drm_device *dev); > const char *zapfw; > > -- > 2.34.1 >
On Wed, Nov 20, 2024 at 3:18 AM Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote: > > On Tue, Nov 19, 2024 at 06:56:38PM +0100, Neil Armstrong wrote: > > Now the features defines have the right name, introduce a features > > bitfield and move the features defines in it, fixing all code checking > > for them. > > > > No functional changes intended. > > I think it might be better to squahs this patch into the previous one, > it would simplify checking that we use .quirks for ADRENO_QUIRK_foo and > .features for ADRENO_FEAT_bar. > IMHO better to keep this separated But we don't have _that_ many features/quirks so I don't find combining them all that problematic BR, -R > > > > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > > --- > > drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 34 +++++++++++++++--------------- > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4 ++-- > > drivers/gpu/drm/msm/adreno/adreno_device.c | 2 +- > > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 7 +++--- > > 4 files changed, 24 insertions(+), 23 deletions(-) > > > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > > index 825c820def315968d508973c8ae40c7c7b646569..93f0d4bf50ba773ecde93e6c29a2fcec24ebb7b3 100644 > > --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > > @@ -743,7 +743,7 @@ static const struct adreno_info a6xx_gpus[] = { > > }, > > .gmem = SZ_512K, > > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT, > > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT, > > .init = a6xx_gpu_init, > > .zapfw = "a615_zap.mbn", > > .a6xx = &(const struct a6xx_info) { > > @@ -769,7 +769,7 @@ static const struct adreno_info a6xx_gpus[] = { > > }, > > .gmem = SZ_512K, > > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT, > > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT, > > .init = a6xx_gpu_init, > > .a6xx = &(const struct a6xx_info) { > > .protect = &a630_protect, > > @@ -839,7 +839,7 @@ static const struct adreno_info a6xx_gpus[] = { > > }, > > .gmem = SZ_512K, > > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT, > > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT, > > .init = a6xx_gpu_init, > > .zapfw = "a615_zap.mdt", > > .a6xx = &(const struct a6xx_info) { > > @@ -864,7 +864,7 @@ static const struct adreno_info a6xx_gpus[] = { > > }, > > .gmem = SZ_512K, > > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | > > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | > > ADRENO_FEAT_HAS_HW_APRIV, > > .init = a6xx_gpu_init, > > .zapfw = "a620_zap.mbn", > > @@ -892,7 +892,7 @@ static const struct adreno_info a6xx_gpus[] = { > > }, > > .gmem = SZ_1M, > > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT, > > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT, > > .init = a6xx_gpu_init, > > .zapfw = "a630_zap.mdt", > > .a6xx = &(const struct a6xx_info) { > > @@ -911,7 +911,7 @@ static const struct adreno_info a6xx_gpus[] = { > > }, > > .gmem = SZ_1M, > > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT, > > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT, > > .init = a6xx_gpu_init, > > .zapfw = "a640_zap.mdt", > > .a6xx = &(const struct a6xx_info) { > > @@ -934,7 +934,7 @@ static const struct adreno_info a6xx_gpus[] = { > > }, > > .gmem = SZ_1M + SZ_128K, > > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | > > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | > > ADRENO_FEAT_HAS_HW_APRIV, > > .init = a6xx_gpu_init, > > .zapfw = "a650_zap.mdt", > > @@ -961,7 +961,7 @@ static const struct adreno_info a6xx_gpus[] = { > > }, > > .gmem = SZ_1M + SZ_512K, > > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | > > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | > > ADRENO_FEAT_HAS_HW_APRIV, > > .init = a6xx_gpu_init, > > .zapfw = "a660_zap.mdt", > > @@ -981,7 +981,7 @@ static const struct adreno_info a6xx_gpus[] = { > > }, > > .gmem = SZ_1M + SZ_512K, > > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | > > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | > > ADRENO_FEAT_HAS_HW_APRIV, > > .init = a6xx_gpu_init, > > .a6xx = &(const struct a6xx_info) { > > @@ -1000,7 +1000,7 @@ static const struct adreno_info a6xx_gpus[] = { > > }, > > .gmem = SZ_512K, > > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | > > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | > > ADRENO_FEAT_HAS_HW_APRIV, > > .init = a6xx_gpu_init, > > .zapfw = "a660_zap.mbn", > > @@ -1028,7 +1028,7 @@ static const struct adreno_info a6xx_gpus[] = { > > }, > > .gmem = SZ_2M, > > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT, > > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT, > > .init = a6xx_gpu_init, > > .zapfw = "a640_zap.mdt", > > .a6xx = &(const struct a6xx_info) { > > @@ -1046,7 +1046,7 @@ static const struct adreno_info a6xx_gpus[] = { > > }, > > .gmem = SZ_4M, > > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | > > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | > > ADRENO_FEAT_HAS_HW_APRIV, > > .init = a6xx_gpu_init, > > .zapfw = "a690_zap.mdt", > > @@ -1331,7 +1331,7 @@ static const struct adreno_info a7xx_gpus[] = { > > }, > > .gmem = SZ_128K, > > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > > - .quirks = ADRENO_FEAT_HAS_HW_APRIV, > > + .features = ADRENO_FEAT_HAS_HW_APRIV, > > .init = a6xx_gpu_init, > > .zapfw = "a702_zap.mbn", > > .a6xx = &(const struct a6xx_info) { > > @@ -1355,7 +1355,7 @@ static const struct adreno_info a7xx_gpus[] = { > > }, > > .gmem = SZ_2M, > > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | > > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | > > ADRENO_FEAT_HAS_HW_APRIV | > > ADRENO_FEAT_PREEMPTION, > > .init = a6xx_gpu_init, > > @@ -1377,7 +1377,7 @@ static const struct adreno_info a7xx_gpus[] = { > > }, > > .gmem = 3 * SZ_1M, > > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | > > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | > > ADRENO_FEAT_HAS_HW_APRIV | > > ADRENO_FEAT_PREEMPTION, > > .init = a6xx_gpu_init, > > @@ -1400,7 +1400,7 @@ static const struct adreno_info a7xx_gpus[] = { > > }, > > .gmem = 3 * SZ_1M, > > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | > > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | > > ADRENO_FEAT_HAS_HW_APRIV | > > ADRENO_FEAT_PREEMPTION, > > .init = a6xx_gpu_init, > > @@ -1422,7 +1422,7 @@ static const struct adreno_info a7xx_gpus[] = { > > }, > > .gmem = 3 * SZ_1M, > > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > > - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | > > + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | > > ADRENO_FEAT_HAS_HW_APRIV | > > ADRENO_FEAT_PREEMPTION, > > .init = a6xx_gpu_init, > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > > index 2ebd3fac212576a1507e0b6afe2560cd0408dd89..654d0cff421f15901cd4bf33b41e70004634ec75 100644 > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > > @@ -2478,7 +2478,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) > > adreno_gpu->gmu_is_wrapper = of_device_is_compatible(node, "qcom,adreno-gmu-wrapper"); > > > > adreno_gpu->base.hw_apriv = > > - !!(config->info->quirks & ADRENO_FEAT_HAS_HW_APRIV); > > + !!(config->info->features & ADRENO_FEAT_HAS_HW_APRIV); > > > > /* gpu->info only gets assigned in adreno_gpu_init() */ > > is_a7xx = config->info->family == ADRENO_7XX_GEN1 || > > @@ -2495,7 +2495,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) > > } > > > > if ((enable_preemption == 1) || (enable_preemption == -1 && > > - (config->info->quirks & ADRENO_FEAT_PREEMPTION))) > > + (config->info->features & ADRENO_FEAT_PREEMPTION))) > > ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 4); > > else if (is_a7xx) > > ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 1); > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c > > index 09d4569f77528c2a20cabc814668c4c930dd07f1..11a228472fa0cef3b6e4e21a366470fbbc3ea8df 100644 > > --- a/drivers/gpu/drm/msm/adreno/adreno_device.c > > +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c > > @@ -207,7 +207,7 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) > > > > priv->is_a2xx = info->family < ADRENO_3XX; > > priv->has_cached_coherent = > > - !!(info->quirks & ADRENO_FEAT_HAS_CACHED_COHERENT); > > + !!(info->features & ADRENO_FEAT_HAS_CACHED_COHERENT); > > > > gpu = info->init(drm); > > if (IS_ERR(gpu)) { > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > > index 8782c25e8a393ec7d9dc23ad450908d039bd08c5..4702d4cfca3b58fb3cbb25cb6805f1c19be2ebcb 100644 > > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h > > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > > @@ -55,9 +55,9 @@ enum adreno_family { > > #define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1) > > #define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2) > > > > -#define ADRENO_FEAT_HAS_HW_APRIV BIT(3) > > -#define ADRENO_FEAT_HAS_CACHED_COHERENT BIT(4) > > -#define ADRENO_FEAT_PREEMPTION BIT(5) > > +#define ADRENO_FEAT_HAS_HW_APRIV BIT(0) > > +#define ADRENO_FEAT_HAS_CACHED_COHERENT BIT(1) > > +#define ADRENO_FEAT_PREEMPTION BIT(2) > > > > /* Helper for formating the chip_id in the way that userspace tools like > > * crashdec expect. > > @@ -98,6 +98,7 @@ struct adreno_info { > > uint32_t revn; > > const char *fw[ADRENO_FW_MAX]; > > uint32_t gmem; > > + u64 features; > > u64 quirks; > > struct msm_gpu *(*init)(struct drm_device *dev); > > const char *zapfw; > > > > -- > > 2.34.1 > > > > -- > With best wishes > Dmitry
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index 825c820def315968d508973c8ae40c7c7b646569..93f0d4bf50ba773ecde93e6c29a2fcec24ebb7b3 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -743,7 +743,7 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT, + .features = ADRENO_FEAT_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a615_zap.mbn", .a6xx = &(const struct a6xx_info) { @@ -769,7 +769,7 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT, + .features = ADRENO_FEAT_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .a6xx = &(const struct a6xx_info) { .protect = &a630_protect, @@ -839,7 +839,7 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT, + .features = ADRENO_FEAT_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a615_zap.mdt", .a6xx = &(const struct a6xx_info) { @@ -864,7 +864,7 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | ADRENO_FEAT_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a620_zap.mbn", @@ -892,7 +892,7 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_1M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT, + .features = ADRENO_FEAT_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a630_zap.mdt", .a6xx = &(const struct a6xx_info) { @@ -911,7 +911,7 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_1M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT, + .features = ADRENO_FEAT_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a640_zap.mdt", .a6xx = &(const struct a6xx_info) { @@ -934,7 +934,7 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_1M + SZ_128K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | ADRENO_FEAT_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a650_zap.mdt", @@ -961,7 +961,7 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_1M + SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | ADRENO_FEAT_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a660_zap.mdt", @@ -981,7 +981,7 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_1M + SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | ADRENO_FEAT_HAS_HW_APRIV, .init = a6xx_gpu_init, .a6xx = &(const struct a6xx_info) { @@ -1000,7 +1000,7 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | ADRENO_FEAT_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a660_zap.mbn", @@ -1028,7 +1028,7 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_2M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT, + .features = ADRENO_FEAT_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a640_zap.mdt", .a6xx = &(const struct a6xx_info) { @@ -1046,7 +1046,7 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_4M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | ADRENO_FEAT_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a690_zap.mdt", @@ -1331,7 +1331,7 @@ static const struct adreno_info a7xx_gpus[] = { }, .gmem = SZ_128K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_FEAT_HAS_HW_APRIV, + .features = ADRENO_FEAT_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a702_zap.mbn", .a6xx = &(const struct a6xx_info) { @@ -1355,7 +1355,7 @@ static const struct adreno_info a7xx_gpus[] = { }, .gmem = SZ_2M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | ADRENO_FEAT_HAS_HW_APRIV | ADRENO_FEAT_PREEMPTION, .init = a6xx_gpu_init, @@ -1377,7 +1377,7 @@ static const struct adreno_info a7xx_gpus[] = { }, .gmem = 3 * SZ_1M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | ADRENO_FEAT_HAS_HW_APRIV | ADRENO_FEAT_PREEMPTION, .init = a6xx_gpu_init, @@ -1400,7 +1400,7 @@ static const struct adreno_info a7xx_gpus[] = { }, .gmem = 3 * SZ_1M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | ADRENO_FEAT_HAS_HW_APRIV | ADRENO_FEAT_PREEMPTION, .init = a6xx_gpu_init, @@ -1422,7 +1422,7 @@ static const struct adreno_info a7xx_gpus[] = { }, .gmem = 3 * SZ_1M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | ADRENO_FEAT_HAS_HW_APRIV | ADRENO_FEAT_PREEMPTION, .init = a6xx_gpu_init, diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 2ebd3fac212576a1507e0b6afe2560cd0408dd89..654d0cff421f15901cd4bf33b41e70004634ec75 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2478,7 +2478,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) adreno_gpu->gmu_is_wrapper = of_device_is_compatible(node, "qcom,adreno-gmu-wrapper"); adreno_gpu->base.hw_apriv = - !!(config->info->quirks & ADRENO_FEAT_HAS_HW_APRIV); + !!(config->info->features & ADRENO_FEAT_HAS_HW_APRIV); /* gpu->info only gets assigned in adreno_gpu_init() */ is_a7xx = config->info->family == ADRENO_7XX_GEN1 || @@ -2495,7 +2495,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) } if ((enable_preemption == 1) || (enable_preemption == -1 && - (config->info->quirks & ADRENO_FEAT_PREEMPTION))) + (config->info->features & ADRENO_FEAT_PREEMPTION))) ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 4); else if (is_a7xx) ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 1); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 09d4569f77528c2a20cabc814668c4c930dd07f1..11a228472fa0cef3b6e4e21a366470fbbc3ea8df 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -207,7 +207,7 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) priv->is_a2xx = info->family < ADRENO_3XX; priv->has_cached_coherent = - !!(info->quirks & ADRENO_FEAT_HAS_CACHED_COHERENT); + !!(info->features & ADRENO_FEAT_HAS_CACHED_COHERENT); gpu = info->init(drm); if (IS_ERR(gpu)) { diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 8782c25e8a393ec7d9dc23ad450908d039bd08c5..4702d4cfca3b58fb3cbb25cb6805f1c19be2ebcb 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -55,9 +55,9 @@ enum adreno_family { #define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1) #define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2) -#define ADRENO_FEAT_HAS_HW_APRIV BIT(3) -#define ADRENO_FEAT_HAS_CACHED_COHERENT BIT(4) -#define ADRENO_FEAT_PREEMPTION BIT(5) +#define ADRENO_FEAT_HAS_HW_APRIV BIT(0) +#define ADRENO_FEAT_HAS_CACHED_COHERENT BIT(1) +#define ADRENO_FEAT_PREEMPTION BIT(2) /* Helper for formating the chip_id in the way that userspace tools like * crashdec expect. @@ -98,6 +98,7 @@ struct adreno_info { uint32_t revn; const char *fw[ADRENO_FW_MAX]; uint32_t gmem; + u64 features; u64 quirks; struct msm_gpu *(*init)(struct drm_device *dev); const char *zapfw;
Now the features defines have the right name, introduce a features bitfield and move the features defines in it, fixing all code checking for them. No functional changes intended. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 34 +++++++++++++++--------------- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4 ++-- drivers/gpu/drm/msm/adreno/adreno_device.c | 2 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 7 +++--- 4 files changed, 24 insertions(+), 23 deletions(-)