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Shenoy" CC: Perry Yuan , , , Dhananjay Ugwekar , Mario Limonciello Subject: [PATCH 13/15] cpufreq/amd-pstate: Check if CPPC request has changed before writing to the MSR or shared memory Date: Thu, 5 Dec 2024 16:28:45 -0600 Message-ID: <20241205222847.7889-14-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241205222847.7889-1-mario.limonciello@amd.com> References: <20241205222847.7889-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A349:EE_|DS0PR12MB8455:EE_ X-MS-Office365-Filtering-Correlation-Id: 83e8b0d1-117f-4c1b-fc14-08dd157c3eb3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: U6k3tcpt7ATCvYVZNvCQEimFn5Xn5Ddo3gN9bqbPd10guFBBdeOeP4dP3ZtP3a7vpGo3Xk5yGahZYZGPylOBQ1qgj4YOU4FOXAIre598V/Mv8onQGWREUH3do9dddjga2pqIGbk7lF8/oiy41RTv7XteoE37fDokl0EK/Op6Tb1IxVHZuqMJwMd0xVD1evNZhH7GGdZNhMw6LaX+8Qw0K5ovEqhmGHOU2B2AmMcFkWM+SaUtzh9lLXVH7EkyBmWt8KX100LpZL1lU8f+NKVu441y3/xbdZQ/HFKwfADqPiAXCiKsvC0F4+Zd6cmx9a3RvCkAOik5inXqfMVFq2aFLGD8EqFvNxDoCdzEddi2Jp7USEnb/cfIcsTWN8MZdR53lg4gL6ggI1dR1r2TrcZt15/a5K+C7Q/w48Ln9WcbFX1+Zn64kqQh0j+DZvDSa4YbacqVnHgiX2T+8UxQRRg7WCtwsYjBq97W81zeViTa8KPq6ZYBswhw2vNpazHEe2KjZKqrDkBFL6CXMmV02hK2R5D6QRUETBpNzNGoVAgY//O9ALtMzprDYJm3lwlLm6kh2wBa1/QKpGv6hj9k9TDL2XiSW67AOEbN9y3sXBInLD9ZUpAL8YJVRcwf1udB8NpVhaGqIu9O4r3d8AiYBTksKNA14BEwsHjL5D8QOdARKFtNPvF57vft3MGbG7PElJ26CmkVpa6+qfpft6T7qS6ce7iLhOiYY7XDRvrH+GQ+VxqGqa4KIExwwieQYqIRnxAw6iz7dwHZGCfUd+SDYOvJgEqGmen3/RWlHhx4vUilW3M/Ewowh4dqvlPh/NXsF3+cHy1O+TpP/+GKWhcxWZlAarHl8NswD9fXhLpwT08qRRth9PUpRvkyryT/S3jqse5ztszGkuIFC5+ZNdnizQwGLZ+MnD0BvEIT3/gKLpV74tGRuG4ATz5J6859ov5OFBeyIxozXlH8vzqYwvjcQIYhCef59oHBmCeloQkA//ETdGAi1Hs+2s0GPPBzcIFGjQs4GnCTO1+mt0in9t4NbXjE0vNmC2fc6+SoZfX5iGY/mYkqerL1khxXyx42RlJEgU2EXGWe6RTOCgZ72GbKNuQgHoRigvow9wo8CH2sO4cWmxPWDJOTnhDGRM/DEpAOM3b3ZtBohMJQ+K/zBESQyVssHwvRf/Xam48AIoi/uJwBUjhiKSeSihCE32KmwipU6yaSwDw27+B0YSVnIhZQCcVpHpW0NI4OnvVJWCKPiPlTPHCj96e9mEixO3bF8cj4Fz7tdCDXUe4WchPQFdg5RuQGAFEaHP+twiPp67ykRKddMLQOxx7M5G6b+xBP5F79+FVWKog87Es3/cohO+gsf6aY5SamJrjl/k1L6k/GoqbvB7vjpeQD7JJtdK2RHB50naVeQTv8CJ7KV6u67NW8n48lfgX4LHoVZWVDAMbTRB4MwGX3nmDVO7buMrjH6QqyA5ZZ X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(82310400026)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Dec 2024 22:29:12.7808 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 83e8b0d1-117f-4c1b-fc14-08dd157c3eb3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A349.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8455 Move the common MSR field formatting code to msr_update_perf() from its callers. Ensure that the MSR write is necessary before flushing a write out. Also drop the comparison from the passive flow tracing. Signed-off-by: Mario Limonciello --- drivers/cpufreq/amd-pstate-trace.h | 7 +---- drivers/cpufreq/amd-pstate.c | 47 +++++++++++------------------- 2 files changed, 18 insertions(+), 36 deletions(-) diff --git a/drivers/cpufreq/amd-pstate-trace.h b/drivers/cpufreq/amd-pstate-trace.h index e2221a4b6901c..8d692415d9050 100644 --- a/drivers/cpufreq/amd-pstate-trace.h +++ b/drivers/cpufreq/amd-pstate-trace.h @@ -32,7 +32,6 @@ TRACE_EVENT(amd_pstate_perf, u64 aperf, u64 tsc, unsigned int cpu_id, - bool changed, bool fast_switch ), @@ -44,7 +43,6 @@ TRACE_EVENT(amd_pstate_perf, aperf, tsc, cpu_id, - changed, fast_switch ), @@ -57,7 +55,6 @@ TRACE_EVENT(amd_pstate_perf, __field(unsigned long long, aperf) __field(unsigned long long, tsc) __field(unsigned int, cpu_id) - __field(bool, changed) __field(bool, fast_switch) ), @@ -70,11 +67,10 @@ TRACE_EVENT(amd_pstate_perf, __entry->aperf = aperf; __entry->tsc = tsc; __entry->cpu_id = cpu_id; - __entry->changed = changed; __entry->fast_switch = fast_switch; ), - TP_printk("amd_min_perf=%lu amd_des_perf=%lu amd_max_perf=%lu freq=%llu mperf=%llu aperf=%llu tsc=%llu cpu_id=%u changed=%s fast_switch=%s", + TP_printk("amd_min_perf=%lu amd_des_perf=%lu amd_max_perf=%lu freq=%llu mperf=%llu aperf=%llu tsc=%llu cpu_id=%u fast_switch=%s", (unsigned long)__entry->min_perf, (unsigned long)__entry->target_perf, (unsigned long)__entry->capacity, @@ -83,7 +79,6 @@ TRACE_EVENT(amd_pstate_perf, (unsigned long long)__entry->aperf, (unsigned long long)__entry->tsc, (unsigned int)__entry->cpu_id, - (__entry->changed) ? "true" : "false", (__entry->fast_switch) ? "true" : "false" ) ); diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 8598f50e18b58..06464e2dd905f 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -224,15 +224,26 @@ static s16 shmem_get_epp(struct amd_cpudata *cpudata) static int msr_update_perf(struct amd_cpudata *cpudata, u32 min_perf, u32 des_perf, u32 max_perf, u32 epp, bool fast_switch) { - u64 value; + u64 value, prev; + + value = prev = READ_ONCE(cpudata->cppc_req_cached); + + value &= ~(AMD_PSTATE_MAX_PERF_MASK | AMD_PSTATE_MIN_PERF_MASK | + AMD_PSTATE_DES_PERF_MASK | AMD_PSTATE_EPP_PERF_MASK); + value |= FIELD_PREP(AMD_PSTATE_MAX_PERF_MASK, max_perf); + value |= FIELD_PREP(AMD_PSTATE_DES_PERF_MASK, des_perf); + value |= FIELD_PREP(AMD_PSTATE_MIN_PERF_MASK, min_perf); + value |= FIELD_PREP(AMD_PSTATE_EPP_PERF_MASK, epp); + + if (value == prev) + return 0; - value = READ_ONCE(cpudata->cppc_req_cached); if (fast_switch) { - wrmsrl(MSR_AMD_CPPC_REQ, READ_ONCE(cpudata->cppc_req_cached)); + wrmsrl(MSR_AMD_CPPC_REQ, value); return 0; } else { - int ret = wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, - READ_ONCE(cpudata->cppc_req_cached)); + int ret = wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); + if (ret) return ret; } @@ -528,9 +539,7 @@ static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf, { unsigned long max_freq; struct cpufreq_policy *policy = cpufreq_cpu_get(cpudata->cpu); - u64 prev = READ_ONCE(cpudata->cppc_req_cached); u32 nominal_perf = READ_ONCE(cpudata->nominal_perf); - u64 value = prev; des_perf = clamp_t(unsigned long, des_perf, min_perf, max_perf); @@ -546,27 +555,14 @@ static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf, if (!cpudata->boost_supported) max_perf = min_t(unsigned long, nominal_perf, max_perf); - value &= ~(AMD_PSTATE_MAX_PERF_MASK | AMD_PSTATE_MIN_PERF_MASK | - AMD_PSTATE_DES_PERF_MASK); - value |= FIELD_PREP(AMD_PSTATE_MAX_PERF_MASK, max_perf); - value |= FIELD_PREP(AMD_PSTATE_DES_PERF_MASK, des_perf); - value |= FIELD_PREP(AMD_PSTATE_MIN_PERF_MASK, min_perf); - if (trace_amd_pstate_perf_enabled() && amd_pstate_sample(cpudata)) { trace_amd_pstate_perf(min_perf, des_perf, max_perf, cpudata->freq, cpudata->cur.mperf, cpudata->cur.aperf, cpudata->cur.tsc, - cpudata->cpu, (value != prev), fast_switch); + cpudata->cpu, fast_switch); } - if (value == prev) - goto cpufreq_policy_put; - - WRITE_ONCE(cpudata->cppc_req_cached, value); - amd_pstate_update_perf(cpudata, min_perf, des_perf, max_perf, 0, fast_switch); -cpufreq_policy_put: - cpufreq_cpu_put(policy); } @@ -1564,19 +1560,10 @@ static void amd_pstate_epp_cpu_exit(struct cpufreq_policy *policy) static int amd_pstate_epp_update_limit(struct cpufreq_policy *policy) { struct amd_cpudata *cpudata = policy->driver_data; - u64 value; u32 epp; amd_pstate_update_min_max_limit(policy); - value = READ_ONCE(cpudata->cppc_req_cached); - - value &= ~(AMD_PSTATE_MAX_PERF_MASK | AMD_PSTATE_MIN_PERF_MASK | - AMD_PSTATE_DES_PERF_MASK | AMD_PSTATE_EPP_PERF_MASK); - value |= FIELD_PREP(AMD_PSTATE_MAX_PERF_MASK, cpudata->max_limit_perf); - value |= FIELD_PREP(AMD_PSTATE_DES_PERF_MASK, 0); - value |= FIELD_PREP(AMD_PSTATE_MIN_PERF_MASK, cpudata->min_limit_perf); - if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) epp = 0; else