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Shenoy" CC: Perry Yuan , , , Dhananjay Ugwekar , Mario Limonciello Subject: [PATCH v2 06/16] cpufreq/amd-pstate: Use FIELD_PREP and FIELD_GET macros Date: Sun, 8 Dec 2024 00:30:21 -0600 Message-ID: <20241208063031.3113-7-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241208063031.3113-1-mario.limonciello@amd.com> References: <20241208063031.3113-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D8:EE_|IA1PR12MB7520:EE_ X-MS-Office365-Filtering-Correlation-Id: d1f493ef-5b00-4cab-639a-08dd1751df7a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: w//cFdOE37yygib4glWmp59LHx/f0xvJ6LeWKeCLc4uAjbmn52phyr4tP6QQIqofBGuy5yeKJ2sXH7trOv39UQO4AbvAlrtHiea64WzNznT03CfaL44lJ76ixgUX35DNp9I3b76Ez5IcXYZcz0mNCAZ5KqXhpwvaUF1o1bHATKVlJ9eiKwb2qPBO2cjYmaBRSDyMeYJjDMmbBtQHwxpm+4KRwlQFoH0MdDkEucL33H61T0pvfHo05jVStSZnaQVRJKcjFh5n5wiBv/YucEkFFWq6nqqzCYjm8HWjRZ4ScknCrjdqaq4RDsObH7w0nWWcQvmopCRrNDe3JoRSPpEA6+0p/oLDzP8lCp6W9/7S4Zk4faQbySibhOA/6318APDodzrdw6PRBUsSYYaf9Akr8ZUzWRTQKR1hHDW6PFnAytji3gPJdE5K7+4jb9UMZUqNdnchuiQxfhmRB6QiywMI1paDA8DVY5lUTx0bc7ObSVaBLKPTRhRAtqkObV7MybOLAu4Dg3vCiKNjIrW78FX91dgFjrilH0rCpxdqH6ix1KpPNHyNg4RAcOJwgzPDQCUqwr+pEvKREmGeoYs3iBGTMyyLeb8IjshXMvoOxbnBt58YyUlKR/8b4qWyGpewbpOqNiQEgA8saVFOSr4vnqakO83jt3v06fTXb28dxfj6xhSBPJohmiXzOXDVJQ+HHf5Q1PTV/6UjoFvCQyqrHxrw5oGmRQNZoofuixH1xYuQmNA60dc2SnZOS/oFCW1bVheBOPfdev3z/XuCRil3iNMLCpK9ZpAeFGTpGHZtJbVAnpwQa5FA3Yp/wKkxIl89s6kmawA40qgIekf57Z6vz6MiPtO6IyPWEcIFELTQEhYIvzlqqpUZGgpkQTI1p4XWVA/fsnEIDkxF/nAq088QKD+2UvNW/64WoZBrbcXO0DYrB+ql8DJHhS02NOJryG2O27zquAEBNUWP1WyBxLopRNRo3NfYblbO8HyL8oU5IvjKpenn2uQxPJH926VwuelLZOOsaWE8bR5N1ZO3QuJccfvtXRuKXP4gfnitBG0lUN8vqOkHOK9QQKdKWQsvtE7qfS+YL7zbPIU0JsRUTTUEV4OWAmmKURQgygewO8r/LjR9p5cq+F1x86P7TzcCmoPxOdX6lv5K/d5OPFji29OML5lIgMVUlrJalvJfZtW28D8Is+gQD5k3rTMRU9/t8VbANxGep8Zl722OIVocV9DDviRzgWWEhU52yNXLxXW2HKimsYXbJQv85LVoRU52Jni2dhnZ1eJOhC6Ykl+Hix8TvJbPALRgi3/o2yA3qOsNVW2iyQ/Kl1UMSwomLpVxSjr0F9Hfs2zuQ4iBWsTGOv2Bf2xAyvoKVMBCydyzl4HQzKh64x9HHjHDFSuPZm/6dErAwKUhqo2ESLft1LzP5vC0OcTMpyqeE4G4O8o15Xhf3NAcC+w3VQpQvMAGm2w7BpVNNXow X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(82310400026)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Dec 2024 06:30:56.3889 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d1f493ef-5b00-4cab-639a-08dd1751df7a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7520 The FIELD_PREP and FIELD_GET macros improve readability and help to avoid shifting bugs. Reviewed-by: Gautham R. Shenoy Signed-off-by: Mario Limonciello --- v2: * Add a missing case to traces * Use AMD_CPPC instead of AMD_PSTATE --- drivers/cpufreq/amd-pstate.c | 51 ++++++++++++++++-------------------- 1 file changed, 23 insertions(+), 28 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index dd25e7e615984..0ed04316a8d80 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -22,6 +22,7 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt +#include #include #include #include @@ -88,6 +89,11 @@ static bool cppc_enabled; static bool amd_pstate_prefcore = true; static struct quirk_entry *quirks; +#define AMD_CPPC_MAX_PERF_MASK GENMASK(7, 0) +#define AMD_CPPC_MIN_PERF_MASK GENMASK(15, 8) +#define AMD_CPPC_DES_PERF_MASK GENMASK(23, 16) +#define AMD_CPPC_EPP_PERF_MASK GENMASK(31, 24) + /* * AMD Energy Preference Performance (EPP) * The EPP is used in the CCLK DPM controller to drive @@ -182,7 +188,6 @@ static DEFINE_MUTEX(amd_pstate_driver_lock); static s16 msr_get_epp(struct amd_cpudata *cpudata, u64 cppc_req_cached) { - u64 epp; int ret; if (!cppc_req_cached) { @@ -192,9 +197,8 @@ static s16 msr_get_epp(struct amd_cpudata *cpudata, u64 cppc_req_cached) return ret; } } - epp = (cppc_req_cached >> 24) & 0xFF; - return (s16)epp; + return FIELD_GET(AMD_CPPC_EPP_PERF_MASK, cppc_req_cached); } DEFINE_STATIC_CALL(amd_pstate_get_epp, msr_get_epp); @@ -269,12 +273,11 @@ static inline void amd_pstate_update_perf(struct amd_cpudata *cpudata, static int msr_set_epp(struct amd_cpudata *cpudata, u32 epp) { - int ret; - u64 value = READ_ONCE(cpudata->cppc_req_cached); + int ret; - value &= ~GENMASK_ULL(31, 24); - value |= (u64)epp << 24; + value &= ~AMD_CPPC_EPP_PERF_MASK; + value |= FIELD_PREP(AMD_CPPC_EPP_PERF_MASK, epp); WRITE_ONCE(cpudata->cppc_req_cached, value); ret = wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); @@ -327,8 +330,8 @@ static int amd_pstate_set_energy_pref_index(struct amd_cpudata *cpudata, if (trace_amd_pstate_epp_perf_enabled()) { trace_amd_pstate_epp_perf(cpudata->cpu, cpudata->highest_perf, epp, - AMD_CPPC_MIN_PERF(cpudata->cppc_req_cached), - AMD_CPPC_MAX_PERF(cpudata->cppc_req_cached), + FIELD_GET(AMD_CPPC_MIN_PERF_MASK, cpudata->cppc_req_cached), + FIELD_GET(AMD_CPPC_MAX_PERF_MASK, cpudata->cppc_req_cached), cpudata->boost_state); } @@ -542,18 +545,15 @@ static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf, des_perf = 0; } - value &= ~AMD_CPPC_MIN_PERF(~0L); - value |= AMD_CPPC_MIN_PERF(min_perf); - - value &= ~AMD_CPPC_DES_PERF(~0L); - value |= AMD_CPPC_DES_PERF(des_perf); - /* limit the max perf when core performance boost feature is disabled */ if (!cpudata->boost_supported) max_perf = min_t(unsigned long, nominal_perf, max_perf); - value &= ~AMD_CPPC_MAX_PERF(~0L); - value |= AMD_CPPC_MAX_PERF(max_perf); + value &= ~(AMD_CPPC_MAX_PERF_MASK | AMD_CPPC_MIN_PERF_MASK | + AMD_CPPC_DES_PERF_MASK); + value |= FIELD_PREP(AMD_CPPC_MAX_PERF_MASK, max_perf); + value |= FIELD_PREP(AMD_CPPC_DES_PERF_MASK, des_perf); + value |= FIELD_PREP(AMD_CPPC_MIN_PERF_MASK, min_perf); if (trace_amd_pstate_perf_enabled() && amd_pstate_sample(cpudata)) { trace_amd_pstate_perf(min_perf, des_perf, max_perf, cpudata->freq, @@ -1573,16 +1573,11 @@ static int amd_pstate_epp_update_limit(struct cpufreq_policy *policy) if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) min_perf = min(cpudata->nominal_perf, max_perf); - /* Initial min/max values for CPPC Performance Controls Register */ - value &= ~AMD_CPPC_MIN_PERF(~0L); - value |= AMD_CPPC_MIN_PERF(min_perf); - - value &= ~AMD_CPPC_MAX_PERF(~0L); - value |= AMD_CPPC_MAX_PERF(max_perf); - - /* CPPC EPP feature require to set zero to the desire perf bit */ - value &= ~AMD_CPPC_DES_PERF(~0L); - value |= AMD_CPPC_DES_PERF(0); + value &= ~(AMD_CPPC_MAX_PERF_MASK | AMD_CPPC_MIN_PERF_MASK | + AMD_CPPC_DES_PERF_MASK); + value |= FIELD_PREP(AMD_CPPC_MAX_PERF_MASK, max_perf); + value |= FIELD_PREP(AMD_CPPC_DES_PERF_MASK, 0); + value |= FIELD_PREP(AMD_CPPC_MIN_PERF_MASK, min_perf); /* Get BIOS pre-defined epp value */ epp = amd_pstate_get_epp(cpudata, value); @@ -1652,7 +1647,7 @@ static void amd_pstate_epp_reenable(struct amd_cpudata *cpudata) if (trace_amd_pstate_epp_perf_enabled()) { trace_amd_pstate_epp_perf(cpudata->cpu, cpudata->highest_perf, cpudata->epp_cached, - AMD_CPPC_MIN_PERF(cpudata->cppc_req_cached), + FIELD_GET(AMD_CPPC_MIN_PERF_MASK, cpudata->cppc_req_cached), max_perf, cpudata->boost_state); }