diff mbox series

[07/14] cpufreq/amd-pstate: Replace all AMD_CPPC_* macros with masks

Message ID 20250206215659.3350066-8-superm1@kernel.org (mailing list archive)
State Superseded, archived
Delegated to: Mario Limonciello
Headers show
Series amd-pstate cleanups | expand

Commit Message

Mario Limonciello Feb. 6, 2025, 9:56 p.m. UTC 
From: Mario Limonciello <mario.limonciello@amd.com>

Bitfield masks are easier to follow and less error prone.

Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
---
 arch/x86/include/asm/msr-index.h | 18 +++++++++---------
 arch/x86/kernel/acpi/cppc.c      |  2 +-
 drivers/cpufreq/amd-pstate-ut.c  |  8 ++++----
 drivers/cpufreq/amd-pstate.c     | 16 ++++++----------
 4 files changed, 20 insertions(+), 24 deletions(-)

Comments

Dhananjay Ugwekar Feb. 11, 2025, 6:16 a.m. UTC | #1 
On 2/7/2025 3:26 AM, Mario Limonciello wrote:
> From: Mario Limonciello <mario.limonciello@amd.com>
> 
> Bitfield masks are easier to follow and less error prone.

Looks good to me, just one suggestion below, apart from that,

Reviewed-by: Dhananjay Ugwekar <dhananjay.ugwekar@amd.com>

> 
> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
> ---
>  arch/x86/include/asm/msr-index.h | 18 +++++++++---------
>  arch/x86/kernel/acpi/cppc.c      |  2 +-
>  drivers/cpufreq/amd-pstate-ut.c  |  8 ++++----
>  drivers/cpufreq/amd-pstate.c     | 16 ++++++----------
>  4 files changed, 20 insertions(+), 24 deletions(-)
> 
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index 3eadc4d5de837..f77335ebae981 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -700,15 +700,15 @@
>  #define MSR_AMD_CPPC_REQ		0xc00102b3
>  #define MSR_AMD_CPPC_STATUS		0xc00102b4
>  
> -#define AMD_CPPC_LOWEST_PERF(x)		(((x) >> 0) & 0xff)
> -#define AMD_CPPC_LOWNONLIN_PERF(x)	(((x) >> 8) & 0xff)
> -#define AMD_CPPC_NOMINAL_PERF(x)	(((x) >> 16) & 0xff)
> -#define AMD_CPPC_HIGHEST_PERF(x)	(((x) >> 24) & 0xff)
> -
> -#define AMD_CPPC_MAX_PERF(x)		(((x) & 0xff) << 0)
> -#define AMD_CPPC_MIN_PERF(x)		(((x) & 0xff) << 8)
> -#define AMD_CPPC_DES_PERF(x)		(((x) & 0xff) << 16)
> -#define AMD_CPPC_ENERGY_PERF_PREF(x)	(((x) & 0xff) << 24)
> +#define AMD_CPPC_LOWEST_PERF_MASK	GENMASK(7, 0)

How about  AMD_CPPC_"CAP"_LOWEST_PERF_MASK and

> +#define AMD_CPPC_LOWNONLIN_PERF_MASK	GENMASK(15, 8)
> +#define AMD_CPPC_NOMINAL_PERF_MASK	GENMASK(23, 16)
> +#define AMD_CPPC_HIGHEST_PERF_MASK	GENMASK(31, 24)
> +
> +#define AMD_CPPC_MAX_PERF_MASK		GENMASK(7, 0)

	   AMD_CPPC_"REQ"_MAX_PERF_MASK, just to indicate these fields 
belong to which register? But we can keep it as is, if you think it 
would be a mouthful, I'll leave it upto you.

Thanks,
Dhananjay

> +#define AMD_CPPC_MIN_PERF_MASK		GENMASK(15, 8)
> +#define AMD_CPPC_DES_PERF_MASK		GENMASK(23, 16)
> +#define AMD_CPPC_EPP_PERF_MASK		GENMASK(31, 24)
>  
>  /* AMD Performance Counter Global Status and Control MSRs */
>  #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS	0xc0000300
> diff --git a/arch/x86/kernel/acpi/cppc.c b/arch/x86/kernel/acpi/cppc.c
> index d745dd586303c..d68a4cb0168fa 100644
> --- a/arch/x86/kernel/acpi/cppc.c
> +++ b/arch/x86/kernel/acpi/cppc.c
> @@ -149,7 +149,7 @@ int amd_get_highest_perf(unsigned int cpu, u32 *highest_perf)
>  		if (ret)
>  			goto out;
>  
> -		val = AMD_CPPC_HIGHEST_PERF(val);
> +		val = FIELD_GET(AMD_CPPC_HIGHEST_PERF_MASK, val);
>  	} else {
>  		ret = cppc_get_highest_perf(cpu, &val);
>  		if (ret)
> diff --git a/drivers/cpufreq/amd-pstate-ut.c b/drivers/cpufreq/amd-pstate-ut.c
> index adaa62fb2b04e..2595faa492bf1 100644
> --- a/drivers/cpufreq/amd-pstate-ut.c
> +++ b/drivers/cpufreq/amd-pstate-ut.c
> @@ -158,10 +158,10 @@ static void amd_pstate_ut_check_perf(u32 index)
>  				return;
>  			}
>  
> -			highest_perf = AMD_CPPC_HIGHEST_PERF(cap1);
> -			nominal_perf = AMD_CPPC_NOMINAL_PERF(cap1);
> -			lowest_nonlinear_perf = AMD_CPPC_LOWNONLIN_PERF(cap1);
> -			lowest_perf = AMD_CPPC_LOWEST_PERF(cap1);
> +			highest_perf = FIELD_GET(AMD_CPPC_HIGHEST_PERF_MASK, cap1);
> +			nominal_perf = FIELD_GET(AMD_CPPC_NOMINAL_PERF_MASK, cap1);
> +			lowest_nonlinear_perf = FIELD_GET(AMD_CPPC_LOWNONLIN_PERF_MASK, cap1);
> +			lowest_perf = FIELD_GET(AMD_CPPC_LOWEST_PERF_MASK, cap1);
>  		}
>  
>  		if (highest_perf != READ_ONCE(cpudata->perf.highest_perf) &&
> diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
> index 71636bd9884c8..cd96443fc117f 100644
> --- a/drivers/cpufreq/amd-pstate.c
> +++ b/drivers/cpufreq/amd-pstate.c
> @@ -89,11 +89,6 @@ static bool cppc_enabled;
>  static bool amd_pstate_prefcore = true;
>  static struct quirk_entry *quirks;
>  
> -#define AMD_CPPC_MAX_PERF_MASK		GENMASK(7, 0)
> -#define AMD_CPPC_MIN_PERF_MASK		GENMASK(15, 8)
> -#define AMD_CPPC_DES_PERF_MASK		GENMASK(23, 16)
> -#define AMD_CPPC_EPP_PERF_MASK		GENMASK(31, 24)
> -
>  /*
>   * AMD Energy Preference Performance (EPP)
>   * The EPP is used in the CCLK DPM controller to drive
> @@ -445,12 +440,13 @@ static int msr_init_perf(struct amd_cpudata *cpudata)
>  
>  	perf.highest_perf = numerator;
>  	perf.max_limit_perf = numerator;
> -	perf.min_limit_perf = AMD_CPPC_LOWEST_PERF(cap1);
> -	perf.nominal_perf = AMD_CPPC_NOMINAL_PERF(cap1);
> -	perf.lowest_nonlinear_perf = AMD_CPPC_LOWNONLIN_PERF(cap1);
> -	perf.lowest_perf = AMD_CPPC_LOWEST_PERF(cap1);
> +	perf.min_limit_perf = FIELD_GET(AMD_CPPC_LOWEST_PERF_MASK, cap1);
> +	perf.nominal_perf = FIELD_GET(AMD_CPPC_NOMINAL_PERF_MASK, cap1);
> +	perf.lowest_nonlinear_perf = FIELD_GET(AMD_CPPC_LOWNONLIN_PERF_MASK, cap1);
> +	perf.lowest_perf = FIELD_GET(AMD_CPPC_LOWEST_PERF_MASK, cap1);
>  	WRITE_ONCE(cpudata->perf, perf);
> -	WRITE_ONCE(cpudata->prefcore_ranking, AMD_CPPC_HIGHEST_PERF(cap1));
> +	WRITE_ONCE(cpudata->prefcore_ranking, FIELD_GET(AMD_CPPC_HIGHEST_PERF_MASK, cap1));
> +
>  	return 0;
>  }
>
Mario Limonciello Feb. 11, 2025, 6:31 p.m. UTC | #2 
On 2/11/2025 00:16, Dhananjay Ugwekar wrote:
> On 2/7/2025 3:26 AM, Mario Limonciello wrote:
>> From: Mario Limonciello <mario.limonciello@amd.com>
>>
>> Bitfield masks are easier to follow and less error prone.
> 
> Looks good to me, just one suggestion below, apart from that,
> 
> Reviewed-by: Dhananjay Ugwekar <dhananjay.ugwekar@amd.com>
> 
>>
>> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
>> ---
>>   arch/x86/include/asm/msr-index.h | 18 +++++++++---------
>>   arch/x86/kernel/acpi/cppc.c      |  2 +-
>>   drivers/cpufreq/amd-pstate-ut.c  |  8 ++++----
>>   drivers/cpufreq/amd-pstate.c     | 16 ++++++----------
>>   4 files changed, 20 insertions(+), 24 deletions(-)
>>
>> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
>> index 3eadc4d5de837..f77335ebae981 100644
>> --- a/arch/x86/include/asm/msr-index.h
>> +++ b/arch/x86/include/asm/msr-index.h
>> @@ -700,15 +700,15 @@
>>   #define MSR_AMD_CPPC_REQ		0xc00102b3
>>   #define MSR_AMD_CPPC_STATUS		0xc00102b4
>>   
>> -#define AMD_CPPC_LOWEST_PERF(x)		(((x) >> 0) & 0xff)
>> -#define AMD_CPPC_LOWNONLIN_PERF(x)	(((x) >> 8) & 0xff)
>> -#define AMD_CPPC_NOMINAL_PERF(x)	(((x) >> 16) & 0xff)
>> -#define AMD_CPPC_HIGHEST_PERF(x)	(((x) >> 24) & 0xff)
>> -
>> -#define AMD_CPPC_MAX_PERF(x)		(((x) & 0xff) << 0)
>> -#define AMD_CPPC_MIN_PERF(x)		(((x) & 0xff) << 8)
>> -#define AMD_CPPC_DES_PERF(x)		(((x) & 0xff) << 16)
>> -#define AMD_CPPC_ENERGY_PERF_PREF(x)	(((x) & 0xff) << 24)
>> +#define AMD_CPPC_LOWEST_PERF_MASK	GENMASK(7, 0)
> 
> How about  AMD_CPPC_"CAP"_LOWEST_PERF_MASK and
> 
>> +#define AMD_CPPC_LOWNONLIN_PERF_MASK	GENMASK(15, 8)
>> +#define AMD_CPPC_NOMINAL_PERF_MASK	GENMASK(23, 16)
>> +#define AMD_CPPC_HIGHEST_PERF_MASK	GENMASK(31, 24)
>> +
>> +#define AMD_CPPC_MAX_PERF_MASK		GENMASK(7, 0)
> 
> 	   AMD_CPPC_"REQ"_MAX_PERF_MASK, just to indicate these fields
> belong to which register? But we can keep it as is, if you think it
> would be a mouthful, I'll leave it upto you.

I'll split the difference and include a comment around them to indicate 
what they're for.

> 
> Thanks,
> Dhananjay
> 
>> +#define AMD_CPPC_MIN_PERF_MASK		GENMASK(15, 8)
>> +#define AMD_CPPC_DES_PERF_MASK		GENMASK(23, 16)
>> +#define AMD_CPPC_EPP_PERF_MASK		GENMASK(31, 24)
>>   
>>   /* AMD Performance Counter Global Status and Control MSRs */
>>   #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS	0xc0000300
>> diff --git a/arch/x86/kernel/acpi/cppc.c b/arch/x86/kernel/acpi/cppc.c
>> index d745dd586303c..d68a4cb0168fa 100644
>> --- a/arch/x86/kernel/acpi/cppc.c
>> +++ b/arch/x86/kernel/acpi/cppc.c
>> @@ -149,7 +149,7 @@ int amd_get_highest_perf(unsigned int cpu, u32 *highest_perf)
>>   		if (ret)
>>   			goto out;
>>   
>> -		val = AMD_CPPC_HIGHEST_PERF(val);
>> +		val = FIELD_GET(AMD_CPPC_HIGHEST_PERF_MASK, val);
>>   	} else {
>>   		ret = cppc_get_highest_perf(cpu, &val);
>>   		if (ret)
>> diff --git a/drivers/cpufreq/amd-pstate-ut.c b/drivers/cpufreq/amd-pstate-ut.c
>> index adaa62fb2b04e..2595faa492bf1 100644
>> --- a/drivers/cpufreq/amd-pstate-ut.c
>> +++ b/drivers/cpufreq/amd-pstate-ut.c
>> @@ -158,10 +158,10 @@ static void amd_pstate_ut_check_perf(u32 index)
>>   				return;
>>   			}
>>   
>> -			highest_perf = AMD_CPPC_HIGHEST_PERF(cap1);
>> -			nominal_perf = AMD_CPPC_NOMINAL_PERF(cap1);
>> -			lowest_nonlinear_perf = AMD_CPPC_LOWNONLIN_PERF(cap1);
>> -			lowest_perf = AMD_CPPC_LOWEST_PERF(cap1);
>> +			highest_perf = FIELD_GET(AMD_CPPC_HIGHEST_PERF_MASK, cap1);
>> +			nominal_perf = FIELD_GET(AMD_CPPC_NOMINAL_PERF_MASK, cap1);
>> +			lowest_nonlinear_perf = FIELD_GET(AMD_CPPC_LOWNONLIN_PERF_MASK, cap1);
>> +			lowest_perf = FIELD_GET(AMD_CPPC_LOWEST_PERF_MASK, cap1);
>>   		}
>>   
>>   		if (highest_perf != READ_ONCE(cpudata->perf.highest_perf) &&
>> diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
>> index 71636bd9884c8..cd96443fc117f 100644
>> --- a/drivers/cpufreq/amd-pstate.c
>> +++ b/drivers/cpufreq/amd-pstate.c
>> @@ -89,11 +89,6 @@ static bool cppc_enabled;
>>   static bool amd_pstate_prefcore = true;
>>   static struct quirk_entry *quirks;
>>   
>> -#define AMD_CPPC_MAX_PERF_MASK		GENMASK(7, 0)
>> -#define AMD_CPPC_MIN_PERF_MASK		GENMASK(15, 8)
>> -#define AMD_CPPC_DES_PERF_MASK		GENMASK(23, 16)
>> -#define AMD_CPPC_EPP_PERF_MASK		GENMASK(31, 24)
>> -
>>   /*
>>    * AMD Energy Preference Performance (EPP)
>>    * The EPP is used in the CCLK DPM controller to drive
>> @@ -445,12 +440,13 @@ static int msr_init_perf(struct amd_cpudata *cpudata)
>>   
>>   	perf.highest_perf = numerator;
>>   	perf.max_limit_perf = numerator;
>> -	perf.min_limit_perf = AMD_CPPC_LOWEST_PERF(cap1);
>> -	perf.nominal_perf = AMD_CPPC_NOMINAL_PERF(cap1);
>> -	perf.lowest_nonlinear_perf = AMD_CPPC_LOWNONLIN_PERF(cap1);
>> -	perf.lowest_perf = AMD_CPPC_LOWEST_PERF(cap1);
>> +	perf.min_limit_perf = FIELD_GET(AMD_CPPC_LOWEST_PERF_MASK, cap1);
>> +	perf.nominal_perf = FIELD_GET(AMD_CPPC_NOMINAL_PERF_MASK, cap1);
>> +	perf.lowest_nonlinear_perf = FIELD_GET(AMD_CPPC_LOWNONLIN_PERF_MASK, cap1);
>> +	perf.lowest_perf = FIELD_GET(AMD_CPPC_LOWEST_PERF_MASK, cap1);
>>   	WRITE_ONCE(cpudata->perf, perf);
>> -	WRITE_ONCE(cpudata->prefcore_ranking, AMD_CPPC_HIGHEST_PERF(cap1));
>> +	WRITE_ONCE(cpudata->prefcore_ranking, FIELD_GET(AMD_CPPC_HIGHEST_PERF_MASK, cap1));
>> +
>>   	return 0;
>>   }
>>   
>
diff mbox series

Patch

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 3eadc4d5de837..f77335ebae981 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -700,15 +700,15 @@ 
 #define MSR_AMD_CPPC_REQ		0xc00102b3
 #define MSR_AMD_CPPC_STATUS		0xc00102b4
 
-#define AMD_CPPC_LOWEST_PERF(x)		(((x) >> 0) & 0xff)
-#define AMD_CPPC_LOWNONLIN_PERF(x)	(((x) >> 8) & 0xff)
-#define AMD_CPPC_NOMINAL_PERF(x)	(((x) >> 16) & 0xff)
-#define AMD_CPPC_HIGHEST_PERF(x)	(((x) >> 24) & 0xff)
-
-#define AMD_CPPC_MAX_PERF(x)		(((x) & 0xff) << 0)
-#define AMD_CPPC_MIN_PERF(x)		(((x) & 0xff) << 8)
-#define AMD_CPPC_DES_PERF(x)		(((x) & 0xff) << 16)
-#define AMD_CPPC_ENERGY_PERF_PREF(x)	(((x) & 0xff) << 24)
+#define AMD_CPPC_LOWEST_PERF_MASK	GENMASK(7, 0)
+#define AMD_CPPC_LOWNONLIN_PERF_MASK	GENMASK(15, 8)
+#define AMD_CPPC_NOMINAL_PERF_MASK	GENMASK(23, 16)
+#define AMD_CPPC_HIGHEST_PERF_MASK	GENMASK(31, 24)
+
+#define AMD_CPPC_MAX_PERF_MASK		GENMASK(7, 0)
+#define AMD_CPPC_MIN_PERF_MASK		GENMASK(15, 8)
+#define AMD_CPPC_DES_PERF_MASK		GENMASK(23, 16)
+#define AMD_CPPC_EPP_PERF_MASK		GENMASK(31, 24)
 
 /* AMD Performance Counter Global Status and Control MSRs */
 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS	0xc0000300
diff --git a/arch/x86/kernel/acpi/cppc.c b/arch/x86/kernel/acpi/cppc.c
index d745dd586303c..d68a4cb0168fa 100644
--- a/arch/x86/kernel/acpi/cppc.c
+++ b/arch/x86/kernel/acpi/cppc.c
@@ -149,7 +149,7 @@  int amd_get_highest_perf(unsigned int cpu, u32 *highest_perf)
 		if (ret)
 			goto out;
 
-		val = AMD_CPPC_HIGHEST_PERF(val);
+		val = FIELD_GET(AMD_CPPC_HIGHEST_PERF_MASK, val);
 	} else {
 		ret = cppc_get_highest_perf(cpu, &val);
 		if (ret)
diff --git a/drivers/cpufreq/amd-pstate-ut.c b/drivers/cpufreq/amd-pstate-ut.c
index adaa62fb2b04e..2595faa492bf1 100644
--- a/drivers/cpufreq/amd-pstate-ut.c
+++ b/drivers/cpufreq/amd-pstate-ut.c
@@ -158,10 +158,10 @@  static void amd_pstate_ut_check_perf(u32 index)
 				return;
 			}
 
-			highest_perf = AMD_CPPC_HIGHEST_PERF(cap1);
-			nominal_perf = AMD_CPPC_NOMINAL_PERF(cap1);
-			lowest_nonlinear_perf = AMD_CPPC_LOWNONLIN_PERF(cap1);
-			lowest_perf = AMD_CPPC_LOWEST_PERF(cap1);
+			highest_perf = FIELD_GET(AMD_CPPC_HIGHEST_PERF_MASK, cap1);
+			nominal_perf = FIELD_GET(AMD_CPPC_NOMINAL_PERF_MASK, cap1);
+			lowest_nonlinear_perf = FIELD_GET(AMD_CPPC_LOWNONLIN_PERF_MASK, cap1);
+			lowest_perf = FIELD_GET(AMD_CPPC_LOWEST_PERF_MASK, cap1);
 		}
 
 		if (highest_perf != READ_ONCE(cpudata->perf.highest_perf) &&
diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
index 71636bd9884c8..cd96443fc117f 100644
--- a/drivers/cpufreq/amd-pstate.c
+++ b/drivers/cpufreq/amd-pstate.c
@@ -89,11 +89,6 @@  static bool cppc_enabled;
 static bool amd_pstate_prefcore = true;
 static struct quirk_entry *quirks;
 
-#define AMD_CPPC_MAX_PERF_MASK		GENMASK(7, 0)
-#define AMD_CPPC_MIN_PERF_MASK		GENMASK(15, 8)
-#define AMD_CPPC_DES_PERF_MASK		GENMASK(23, 16)
-#define AMD_CPPC_EPP_PERF_MASK		GENMASK(31, 24)
-
 /*
  * AMD Energy Preference Performance (EPP)
  * The EPP is used in the CCLK DPM controller to drive
@@ -445,12 +440,13 @@  static int msr_init_perf(struct amd_cpudata *cpudata)
 
 	perf.highest_perf = numerator;
 	perf.max_limit_perf = numerator;
-	perf.min_limit_perf = AMD_CPPC_LOWEST_PERF(cap1);
-	perf.nominal_perf = AMD_CPPC_NOMINAL_PERF(cap1);
-	perf.lowest_nonlinear_perf = AMD_CPPC_LOWNONLIN_PERF(cap1);
-	perf.lowest_perf = AMD_CPPC_LOWEST_PERF(cap1);
+	perf.min_limit_perf = FIELD_GET(AMD_CPPC_LOWEST_PERF_MASK, cap1);
+	perf.nominal_perf = FIELD_GET(AMD_CPPC_NOMINAL_PERF_MASK, cap1);
+	perf.lowest_nonlinear_perf = FIELD_GET(AMD_CPPC_LOWNONLIN_PERF_MASK, cap1);
+	perf.lowest_perf = FIELD_GET(AMD_CPPC_LOWEST_PERF_MASK, cap1);
 	WRITE_ONCE(cpudata->perf, perf);
-	WRITE_ONCE(cpudata->prefcore_ranking, AMD_CPPC_HIGHEST_PERF(cap1));
+	WRITE_ONCE(cpudata->prefcore_ranking, FIELD_GET(AMD_CPPC_HIGHEST_PERF_MASK, cap1));
+
 	return 0;
 }