| Message ID | 20250215005244.1212285-15-superm1@kernel.org (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | amd-pstate cleanups | expand |
On Fri, Feb 14, 2025 at 06:52:41PM -0600, Mario Limonciello wrote: > From: Mario Limonciello <mario.limonciello@amd.com> > > On EPP only writes update the cached variable so that the min/max > performance controls don't need to be updated again. This also paves the way to get rid of the cpudata->epp_cached variable which you do in Patch 17. LGTM Reviewed-by: Gautham R. Shenoy <gautham.shenoy@amd.com> > > Reviewed-by: Dhananjay Ugwekar <dhananjay.ugwekar@amd.com> > Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> > --- > drivers/cpufreq/amd-pstate.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c > index 1304bdc23e809..fd2b559f47c5c 100644 > --- a/drivers/cpufreq/amd-pstate.c > +++ b/drivers/cpufreq/amd-pstate.c > @@ -336,6 +336,7 @@ static int shmem_set_epp(struct cpufreq_policy *policy, u8 epp) > { > struct amd_cpudata *cpudata = policy->driver_data; > struct cppc_perf_ctrls perf_ctrls; > + u64 value; > int ret; > > if (trace_amd_pstate_epp_perf_enabled()) { > @@ -362,6 +363,11 @@ static int shmem_set_epp(struct cpufreq_policy *policy, u8 epp) > } > WRITE_ONCE(cpudata->epp_cached, epp); > > + value = READ_ONCE(cpudata->cppc_req_cached); > + value &= ~AMD_CPPC_EPP_PERF_MASK; > + value |= FIELD_PREP(AMD_CPPC_EPP_PERF_MASK, epp); > + WRITE_ONCE(cpudata->cppc_req_cached, value); > + > return ret; > } > > -- > 2.43.0 >
diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 1304bdc23e809..fd2b559f47c5c 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -336,6 +336,7 @@ static int shmem_set_epp(struct cpufreq_policy *policy, u8 epp) { struct amd_cpudata *cpudata = policy->driver_data; struct cppc_perf_ctrls perf_ctrls; + u64 value; int ret; if (trace_amd_pstate_epp_perf_enabled()) { @@ -362,6 +363,11 @@ static int shmem_set_epp(struct cpufreq_policy *policy, u8 epp) } WRITE_ONCE(cpudata->epp_cached, epp); + value = READ_ONCE(cpudata->cppc_req_cached); + value &= ~AMD_CPPC_EPP_PERF_MASK; + value |= FIELD_PREP(AMD_CPPC_EPP_PERF_MASK, epp); + WRITE_ONCE(cpudata->cppc_req_cached, value); + return ret; }