| Message ID | 20250416224839.9840-2-andre.przywara@arm.com (mailing list archive) |
|---|---|
| State | Handled Elsewhere, archived |
| Headers | show |
| Series | arm64: sunxi: h616: Enable Mali GPU | expand |
On Thu, Apr 17, 2025 at 6:49 AM Andre Przywara <andre.przywara@arm.com> wrote: > > The Allwinner H6 and some later SoCs contain some bits in the PRCM (Power > Reset Clock Management) block that control some power domains. > Those power domains include the one for the GPU, the PLLs and some > analogue circuits. > > Signed-off-by: Andre Przywara <andre.przywara@arm.com> > Reviewed-by: Rob Herring (Arm) <robh@kernel.org> > --- > .../power/allwinner,sun50i-h6-prcm-ppu.yaml | 42 +++++++++++++++++++ > 1 file changed, 42 insertions(+) > create mode 100644 Documentation/devicetree/bindings/power/allwinner,sun50i-h6-prcm-ppu.yaml > > diff --git a/Documentation/devicetree/bindings/power/allwinner,sun50i-h6-prcm-ppu.yaml b/Documentation/devicetree/bindings/power/allwinner,sun50i-h6-prcm-ppu.yaml > new file mode 100644 > index 0000000000000..7eaff9baf7268 > --- /dev/null > +++ b/Documentation/devicetree/bindings/power/allwinner,sun50i-h6-prcm-ppu.yaml > @@ -0,0 +1,42 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/power/allwinner,sun50i-h6-prcm-ppu.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Allwinner SoCs PRCM power domain controller > + > +maintainers: > + - Andre Przywara <andre.przywara@arm.com> > + > +description: > + The Allwinner Power Reset Clock Management (PRCM) unit contains bits to > + control a few power domains. > + > +properties: > + compatible: > + enum: > + - allwinner,sun50i-h6-prcm-ppu > + - allwinner,sun50i-h616-prcm-ppu > + - allwinner,sun55i-a523-prcm-ppu > + > + reg: > + maxItems: 1 > + > + '#power-domain-cells': > + const: 1 > + > +required: > + - compatible > + - reg > + - '#power-domain-cells' > + > +additionalProperties: false > + > +examples: > + - | > + prcm_ppu: power-controller@7010210 { This doesn't match the address below. ChenYu > + compatible = "allwinner,sun50i-h616-prcm-ppu"; > + reg = <0x07010250 0x10>; > + #power-domain-cells = <1>; > + }; > -- > 2.46.3 >
diff --git a/Documentation/devicetree/bindings/power/allwinner,sun50i-h6-prcm-ppu.yaml b/Documentation/devicetree/bindings/power/allwinner,sun50i-h6-prcm-ppu.yaml new file mode 100644 index 0000000000000..7eaff9baf7268 --- /dev/null +++ b/Documentation/devicetree/bindings/power/allwinner,sun50i-h6-prcm-ppu.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/allwinner,sun50i-h6-prcm-ppu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner SoCs PRCM power domain controller + +maintainers: + - Andre Przywara <andre.przywara@arm.com> + +description: + The Allwinner Power Reset Clock Management (PRCM) unit contains bits to + control a few power domains. + +properties: + compatible: + enum: + - allwinner,sun50i-h6-prcm-ppu + - allwinner,sun50i-h616-prcm-ppu + - allwinner,sun55i-a523-prcm-ppu + + reg: + maxItems: 1 + + '#power-domain-cells': + const: 1 + +required: + - compatible + - reg + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + prcm_ppu: power-controller@7010210 { + compatible = "allwinner,sun50i-h616-prcm-ppu"; + reg = <0x07010250 0x10>; + #power-domain-cells = <1>; + };