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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN3PEPF0000B078.mail.protection.outlook.com (10.167.243.123) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7544.18 via Frontend Transport; Mon, 6 May 2024 10:20:35 +0000 Received: from pyuan-Chachani-VN.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 6 May 2024 05:20:32 -0500 From: Perry Yuan To: , , , , , CC: , , , , , , Subject: [PATCH v9 6/7] cpufreq: amd-pstate: introduce per CPU frequency boost control Date: Mon, 6 May 2024 18:19:58 +0800 Message-ID: <2d200d0fb4135465e81b9213de940e31a7b88dce.1714989803.git.perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B078:EE_|DS7PR12MB6264:EE_ X-MS-Office365-Filtering-Correlation-Id: 34d5d524-4654-413f-a5d1-08dc6db62b4e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|1800799015|376005|36860700004|82310400017; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 May 2024 10:20:35.7505 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 34d5d524-4654-413f-a5d1-08dc6db62b4e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B078.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6264 Add a new sysfs attribute file to support per CPU frequency boost control, allowing individual CPUs to enable or disable CPB separately. The new sysfs attribute file is located at below path, `/sys/devices/system/cpu/cpuX/cpufreq/amd_pstate_boost_cpb`, where `X` represents the CPU number. To disable CPB for a specific CPU, you can use the following command: $ sudo bash -c "echo 0 > /sys/devices/system/cpu/cpuX/cpufreq/amd_pstate_boost_cpb" After disabling CPB, the CPU frequency will no longer boost beyond the base frequency for that particular CPU. for example: ---------------------------------------------------------------------- CPU NODE SOCKET CORE L1d:L1i:L2:L3 ONLINE MAXMHZ MINMHZ MHZ 0 0 0 0 0:0:0:0 yes 4208.0000 400.0000 1666.7740 1 0 0 0 0:0:0:0 yes 4208.0000 400.0000 400.0000 ---------------------------------------------------------------------- $ sudo bash -c "echo 0 > /sys/devices/system/cpu/cpu0/cpufreq/amd_pstate_boost_cpb" CPU NODE SOCKET CORE L1d:L1i:L2:L3 ONLINE MAXMHZ MINMHZ MHZ 0 0 0 0 0:0:0:0 yes 3501.0000 400.0000 4154.3140 1 0 0 0 0:0:0:0 yes 4208.0000 400.0000 400.0000 Please be aware that modifying the global variable `amd_pstate_global_params.cpb_boost` will overwrite the individual CPU settings. Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 11bce2c1db32..44531711a5fa 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -1371,6 +1371,30 @@ static int amd_pstate_cpu_boost(int cpu, bool state) return ret < 0 ? ret : 0; } +static ssize_t show_amd_pstate_boost_cpb(struct cpufreq_policy *policy, char *buf) +{ + struct amd_cpudata *cpudata = policy->driver_data; + bool boost_val; + + boost_val = READ_ONCE(cpudata->boost_state); + + return sysfs_emit(buf, "%u\n", boost_val); +} + +static ssize_t store_amd_pstate_boost_cpb( + struct cpufreq_policy *policy, const char *buf, size_t count) +{ + bool boost_val; + int ret; + + if (sscanf(buf, "%d", &boost_val) != 1) + return -EINVAL; + + ret = amd_pstate_cpu_boost(policy->cpu, boost_val); + + return ret < 0 ? ret : count; +} + static ssize_t cpb_boost_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -1416,6 +1440,7 @@ cpufreq_freq_attr_ro(amd_pstate_prefcore_ranking); cpufreq_freq_attr_ro(amd_pstate_hw_prefcore); cpufreq_freq_attr_rw(energy_performance_preference); cpufreq_freq_attr_ro(energy_performance_available_preferences); +cpufreq_freq_attr_rw(amd_pstate_boost_cpb); static DEVICE_ATTR_RW(status); static DEVICE_ATTR_RO(prefcore); static DEVICE_ATTR_RW(cpb_boost); @@ -1426,6 +1451,7 @@ static struct freq_attr *amd_pstate_attr[] = { &amd_pstate_highest_perf, &amd_pstate_prefcore_ranking, &amd_pstate_hw_prefcore, + &amd_pstate_boost_cpb, NULL, }; @@ -1437,6 +1463,7 @@ static struct freq_attr *amd_pstate_epp_attr[] = { &amd_pstate_hw_prefcore, &energy_performance_preference, &energy_performance_available_preferences, + &amd_pstate_boost_cpb, NULL, };