From patchwork Tue Aug 19 04:36:36 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vince Hsu X-Patchwork-Id: 4740551 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id D223C9F39D for ; Tue, 19 Aug 2014 04:35:25 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C4D392013A for ; Tue, 19 Aug 2014 04:35:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D81F820123 for ; Tue, 19 Aug 2014 04:35:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751334AbaHSEfW (ORCPT ); Tue, 19 Aug 2014 00:35:22 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:15604 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750997AbaHSEfV (ORCPT ); Tue, 19 Aug 2014 00:35:21 -0400 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Mon, 18 Aug 2014 21:35:28 -0700 Received: from hqemhub01.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Mon, 18 Aug 2014 21:21:40 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Mon, 18 Aug 2014 21:21:40 -0700 Received: from [10.19.108.126] (172.20.144.16) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server id 8.3.342.0; Mon, 18 Aug 2014 21:35:20 -0700 Message-ID: <53F2D454.2020000@nvidia.com> Date: Tue, 19 Aug 2014 12:36:36 +0800 From: Vince Hsu User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 To: Tuomas Tynkkynen , , , , CC: Stephen Warren , Thierry Reding , Peter De Schrijver , Prashant Gaikwad , Mike Turquette , "Rafael J. Wysocki" , Viresh Kumar , Paul Walmsley , , Tuomas Tynkkynen Subject: Re: [PATCH v3 03/15] clk: tegra: Add closed loop support for the DFLL References: <1408419205-10048-1-git-send-email-tuomas.tynkkynen@iki.fi> <1408419205-10048-4-git-send-email-tuomas.tynkkynen@iki.fi> In-Reply-To: <1408419205-10048-4-git-send-email-tuomas.tynkkynen@iki.fi> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Hi, On 08/19/2014 11:33 AM, Tuomas Tynkkynen wrote: > From: Tuomas Tynkkynen > > With closed loop support, the clock rate of the DFLL can be adjusted. > > The oscillator itself in the DFLL is a free-running oscillator whose > rate is directly determined the supply voltage. However, the DFLL > module contains logic to compare the DFLL output rate to a fixed > reference clock (51 MHz) and make a decision to either lower or raise > the DFLL supply voltage. The DFLL module can then autonomously change > the supply voltage by communicating with an off-chip PMIC via either I2C > or PWM signals. This driver currently supports only I2C. > > Signed-off-by: Tuomas Tynkkynen > > --- > v3: Fix incorrect order of arguments to dfll_scale_dvco_rate > --- > drivers/clk/tegra/clk-dfll.c | 656 ++++++++++++++++++++++++++++++++++++++++++- > 1 file changed, 653 insertions(+), 3 deletions(-) ... > + > +/** > + * dfll_init_out_if - prepare DFLL-to-PMIC interface > + * @td: DFLL instance > + * > + * During DFLL driver initialization or resume from context loss, > + * disable the I2C command output to the PMIC, set safe voltage and > + * output limits, and disable and clear limit interrupts. > + */ > +static void dfll_init_out_if(struct tegra_dfll *td) > +{ > + u32 val; > + > + td->lut_min = 0; > + td->lut_max = td->i2c_lut_size - 1; > + td->lut_safe = td->lut_min + 1; > + > + dfll_i2c_writel(td, 0, DFLL_OUTPUT_CFG); > + val = (td->lut_safe << DFLL_OUTPUT_CFG_SAFE_SHIFT) | > + (td->lut_max << DFLL_OUTPUT_CFG_MAX_SHIFT) | > + (td->lut_min << DFLL_OUTPUT_CFG_MIN_SHIFT); > + dfll_writel(td, val, DFLL_OUTPUT_CFG); > + dfll_wmb(td); Sorry that I forgot to mention this in v2's comment. Could you squash the change below in this patch? And actually it's pretty easy to misuse the dfll read/write/wmb functions. We might want to have some generic functions for these, and let the generic functions handle the offset to different register blocks. commit 4a1fdd54141b4f8f9425d54cdad13c42763e6186 Author: Vince Hsu Date: Thu Aug 14 18:19:20 2014 +0800 clk: tegra: use the correct write funtion for DFLL_OUTPUT_CFG Signed-off-by: Vince Hsu seq_puts(s, "\nI2C and INTR REGISTERS:\n"); for (offs = DFLL_I2C_CFG; offs <= DFLL_I2C_STS; offs += 4) Thanks, Vince --- To unsubscribe from this list: send the line "unsubscribe linux-pm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c index 9b3eded6b880..71e4b256ea0d 100644 --- a/drivers/clk/tegra/clk-dfll.c +++ b/drivers/clk/tegra/clk-dfll.c @@ -645,7 +645,7 @@ static void dfll_init_out_if(struct tegra_dfll *td) val = (td->lut_safe << DFLL_OUTPUT_CFG_SAFE_SHIFT) | (td->lut_max << DFLL_OUTPUT_CFG_MAX_SHIFT) | (td->lut_min << DFLL_OUTPUT_CFG_MIN_SHIFT); - dfll_writel(td, val, DFLL_OUTPUT_CFG); + dfll_i2c_writel(td, val, DFLL_OUTPUT_CFG); - dfll_wmb(td); + dfll_i2c_wmb(td); dfll_writel(td, 0, DFLL_OUTPUT_FORCE); @@ -1146,7 +1146,8 @@ static int attr_registers_show(struct seq_file *s, void *data) seq_puts(s, "CONTROL REGISTERS:\n"); for (offs = 0; offs <= DFLL_MONITOR_DATA; offs += 4) seq_printf(s, "[0x%02x] = 0x%08x\n", offs, - dfll_readl(td, offs)); + offs == DFLL_OUTPUT_CFG ? dfll_i2c_readl(td, offs) : + dfll_readl(td, offs));