From patchwork Sat Feb 9 01:08:15 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Len Brown X-Patchwork-Id: 2119441 X-Patchwork-Delegate: lenb@kernel.org Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 149BC3FD56 for ; Sat, 9 Feb 2013 01:10:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932216Ab3BIBKN (ORCPT ); Fri, 8 Feb 2013 20:10:13 -0500 Received: from mail-vc0-f171.google.com ([209.85.220.171]:56734 "EHLO mail-vc0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1947650Ab3BIBIr (ORCPT ); Fri, 8 Feb 2013 20:08:47 -0500 Received: by mail-vc0-f171.google.com with SMTP id p1so2758273vcq.30 for ; Fri, 08 Feb 2013 17:08:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:in-reply-to:references:reply-to:organization; bh=k4GRIXptqsAavderKhYW1Q1SvvUt0Gup+pvtt84NQgk=; b=FlN0x26STLcpOcL3SI8+L3qMYXvYuEvdoxrQ3DVmYIeE60IZ8HnhrVe3Jy4HSo4qOs VRvOaWno8/1zMMaE9MnbzAPEur8DDxdMefKJy+qCtSKJeJTducgW9y/E7T0uRTdxTZ6i zd2QIRcrnO2pwxF/R9223V7Td9+4wwGmAI6iyJ+bkvK4/UCYYR8or1QsYyAYBDw/X5Fc TaABK2hXd1ZL5NSlq2DoC7dS56kToG7etFlGPufIfd29m0v6zujrXrFlz32XdetjDrUl xZdr2FZACMVrmH2CdsEL4TuxgKiW+VPRJ6zsk3yWHbp2MhuQBUimdrNTSFcf4yIayAxx ewLg== X-Received: by 10.220.226.70 with SMTP id iv6mr9371108vcb.9.1360372126995; Fri, 08 Feb 2013 17:08:46 -0800 (PST) Received: from x980.localdomain6 (pool-108-7-58-246.bstnma.fios.verizon.net. [108.7.58.246]) by mx.google.com with ESMTPS id e8sm5806990vdt.7.2013.02.08.17.08.45 (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 08 Feb 2013 17:08:46 -0800 (PST) From: Len Brown To: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Len Brown Subject: [PATCH 11/16] intel_idle: support Haswell Date: Fri, 8 Feb 2013 20:08:15 -0500 Message-Id: <85a4d2d41dc6d1c0296326204a857a9fab864a31.1360371180.git.len.brown@intel.com> X-Mailer: git-send-email 1.8.1.3.535.ga923c31 In-Reply-To: <1360372100-28482-1-git-send-email-lenb@kernel.org> References: <1360372100-28482-1-git-send-email-lenb@kernel.org> In-Reply-To: References: Reply-To: Len Brown Organization: Intel Open Source Technology Center Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Len Brown This patch enables intel_idle to run on the next-generation Intel(R) Microarchitecture code named "Haswell". Signed-off-by: Len Brown --- drivers/idle/intel_idle.c | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c index b2cf489..fa71477 100644 --- a/drivers/idle/intel_idle.c +++ b/drivers/idle/intel_idle.c @@ -212,6 +212,38 @@ static struct cpuidle_state ivb_cstates[MWAIT_MAX_NUM_CSTATES] = { .enter = &intel_idle }, }; +static struct cpuidle_state hsw_cstates[MWAIT_MAX_NUM_CSTATES] = { + { /* MWAIT C0 */ }, + { /* MWAIT C1 */ + .name = "C1-HSW", + .desc = "MWAIT 0x00", + .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, + .exit_latency = 2, + .target_residency = 2, + .enter = &intel_idle }, + { /* MWAIT C2 */ + .name = "C3-HSW", + .desc = "MWAIT 0x10", + .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, + .exit_latency = 33, + .target_residency = 100, + .enter = &intel_idle }, + { /* MWAIT C3 */ + .name = "C6-HSW", + .desc = "MWAIT 0x20", + .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, + .exit_latency = 133, + .target_residency = 400, + .enter = &intel_idle }, + { /* MWAIT C4 */ + .name = "C7s-HSW", + .desc = "MWAIT 0x32", + .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, + .exit_latency = 166, + .target_residency = 500, + .enter = &intel_idle }, +}; + static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = { { /* MWAIT C0 */ }, { /* MWAIT C1 */ @@ -365,6 +397,10 @@ static const struct idle_cpu idle_cpu_ivb = { .state_table = ivb_cstates, }; +static const struct idle_cpu idle_cpu_hsw = { + .state_table = hsw_cstates, +}; + #define ICPU(model, cpu) \ { X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu } @@ -382,6 +418,9 @@ static const struct x86_cpu_id intel_idle_ids[] = { ICPU(0x2d, idle_cpu_snb), ICPU(0x3a, idle_cpu_ivb), ICPU(0x3e, idle_cpu_ivb), + ICPU(0x3c, idle_cpu_hsw), + ICPU(0x3f, idle_cpu_hsw), + ICPU(0x45, idle_cpu_hsw), {} }; MODULE_DEVICE_TABLE(x86cpu, intel_idle_ids);