From patchwork Wed Nov 14 20:43:21 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Len Brown X-Patchwork-Id: 1744051 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 302B1DF264 for ; Wed, 14 Nov 2012 20:45:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755458Ab2KNUni (ORCPT ); Wed, 14 Nov 2012 15:43:38 -0500 Received: from mail-qc0-f174.google.com ([209.85.216.174]:62951 "EHLO mail-qc0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754343Ab2KNUng (ORCPT ); Wed, 14 Nov 2012 15:43:36 -0500 Received: by mail-qc0-f174.google.com with SMTP id o22so558349qcr.19 for ; Wed, 14 Nov 2012 12:43:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:in-reply-to:references:mime-version:content-type :content-transfer-encoding:reply-to:organization; bh=VHf483iWddCjG/PPkF2Ejz9dfeqj/QJ/ZJHEAPzC4RM=; b=UI6KdUg8+qmnI/7n/0AupgJx3FYhyMrJ8qowo9eF0+D6ZrD4UaE/FtZ5R7X+qy14w1 RGaIqU1eTUdEp17ulYpxDw6xZ3dqKsjQp1+FA3kOSCY6D7X3yq/NAx5uAJe7p9OEz53y YbcSSWq+NxXyIrUlrDvVSBo/+CFY4mBB+8pKAxpG/3T1MqcIe7V3tDGD2FDrXKtnD2OZ 9Q6pAiLLY22+GOSqtACVOnYEKSfMbTyi5HItkwtHNIlu69Kp2h2kKmieT36vWtHDPicB croc6pkbDy9HSBgKTMPRlP+cSGFaU/ginTAQM1yNUtOfWCjb6G1YOUFRQ/AWjrjJHXc6 UmuQ== Received: by 10.49.84.130 with SMTP id z2mr23047827qey.22.1352925815673; Wed, 14 Nov 2012 12:43:35 -0800 (PST) Received: from x980.localdomain6 ([173.48.76.143]) by mx.google.com with ESMTPS id f3sm3314272qaj.7.2012.11.14.12.43.34 (version=SSLv3 cipher=OTHER); Wed, 14 Nov 2012 12:43:35 -0800 (PST) From: Len Brown To: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Len Brown , x86@kernel.org Subject: [PATCH 4/7] x86 power: define RAPL MSRs Date: Wed, 14 Nov 2012 15:43:21 -0500 Message-Id: <8e95037d0d9172c87a2b4ebeaff49c4e793ee5d2.1352925508.git.len.brown@intel.com> X-Mailer: git-send-email 1.8.0 In-Reply-To: <1352925804-6746-1-git-send-email-lenb@kernel.org> References: <1352925804-6746-1-git-send-email-lenb@kernel.org> In-Reply-To: <39300ffb9b6666714c60735cf854e1280e4e75f4.1352925508.git.len.brown@intel.com> References: <39300ffb9b6666714c60735cf854e1280e4e75f4.1352925508.git.len.brown@intel.com> MIME-Version: 1.0 Reply-To: Len Brown Organization: Intel Open Source Technology Center Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Len Brown The Run Time Average Power Limiting interface is currently model specific, present on Sandy Bridge and Ivy Bridge processors. These #defines correspond to documentation in the latest "Intel® 64 and IA-32 Architectures Software Developer Manual", plus some typos in that document corrected. Signed-off-by: Len Brown Cc: x86@kernel.org --- arch/x86/include/asm/msr-index.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index c9775a3..7d05006 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -115,6 +115,29 @@ #define MSR_CORE_C7_RESIDENCY 0x000003fe #define MSR_PKG_C2_RESIDENCY 0x0000060d +/* Run Time Average Power Limiting (RAPL) Interface */ + +#define MSR_RAPL_POWER_UNIT 0x00000606 + +#define MSR_PKG_POWER_LIMIT 0x00000610 +#define MSR_PKG_ENERGY_STATUS 0x00000611 +#define MSR_PKG_PERF_STATUS 0x00000613 +#define MSR_PKG_POWER_INFO 0x00000614 + +#define MSR_DRAM_POWER_LIMIT 0x00000618 +#define MSR_DRAM_ENERGY_STATUS 0x00000619 +#define MSR_DRAM_PERF_STATUS 0x0000061b +#define MSR_DRAM_POWER_INFO 0x0000061c + +#define MSR_PP0_POWER_LIMIT 0x00000638 +#define MSR_PP0_ENERGY_STATUS 0x00000639 +#define MSR_PP0_POLICY 0x0000063a +#define MSR_PP0_PERF_STATUS 0x0000063b + +#define MSR_PP1_POWER_LIMIT 0x00000640 +#define MSR_PP1_ENERGY_STATUS 0x00000641 +#define MSR_PP1_POLICY 0x00000642 + #define MSR_AMD64_MC0_MASK 0xc0010044 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))