diff mbox series

[v3,3/6] dt-bindings: devfreq: Add bindings for imx ddr controller

Message ID b9a87c69eb603622303add4f0c02dd4c1262462a.1572558427.git.leonard.crestez@nxp.com (mailing list archive)
State Not Applicable, archived
Headers show
Series PM / devfreq: Add dynamic scaling for imx ddr controller | expand

Commit Message

Leonard Crestez Oct. 31, 2019, 9:50 p.m. UTC
Add devicetree bindings for the i.MX DDR Controller on imx8m series
chips. It supports dynamic frequency switching between multiple data
rates and this is exposed to Linux via the devfreq subsystem.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
---
 .../devicetree/bindings/devfreq/imx-ddrc.yaml | 60 +++++++++++++++++++
 1 file changed, 60 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/devfreq/imx-ddrc.yaml

Comments

Rob Herring (Arm) Nov. 4, 2019, 10:21 p.m. UTC | #1
On Thu, Oct 31, 2019 at 11:50:24PM +0200, Leonard Crestez wrote:
> Add devicetree bindings for the i.MX DDR Controller on imx8m series
> chips. It supports dynamic frequency switching between multiple data
> rates and this is exposed to Linux via the devfreq subsystem.
> 
> Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
> ---
>  .../devicetree/bindings/devfreq/imx-ddrc.yaml | 60 +++++++++++++++++++

.../bindings/memory-controllers/

>  1 file changed, 60 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/devfreq/imx-ddrc.yaml
> 
> diff --git a/Documentation/devicetree/bindings/devfreq/imx-ddrc.yaml b/Documentation/devicetree/bindings/devfreq/imx-ddrc.yaml
> new file mode 100644
> index 000000000000..31db204e6845
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/devfreq/imx-ddrc.yaml
> @@ -0,0 +1,60 @@
> +# SPDX-License-Identifier: GPL-2.0

For new bindings:

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/devfreq/imx-devfreq.yaml#

Run 'make dt_binding_check'. This will fail as the filename doesn't 
match.

> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: i.MX DDR Controller

Perhaps i.MX8x as it's not all i.MX chips. And the filename too?

> +
> +maintainers:
> +  - Leonard Crestez <leonard.crestez@nxp.com>
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +        - fsl,imx8mn-ddrc
> +        - fsl,imx8mm-ddrc
> +        - fsl,imx8mq-ddrc
> +      - const: fsl,imx8m-ddrc
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 4
> +
> +  clock-names:
> +    items:
> +      - const: dram_core
> +      - const: dram_pll
> +      - const: dram_alt
> +      - const: dram_apb

Drop 'dram_'

> +
> +  operating-points-v2: true
> +
> +  devfreq-events:
> +    description: Phandle of PMU node
> +    $ref: "/schemas/types.yaml#/definitions/phandle"
> +
> +required:
> +  - reg
> +  - compatible
> +  - clocks
> +  - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/imx8mm-clock.h>
> +    ddrc: dram-controller@3d400000 {
> +        compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
> +        reg = <0x3d400000 0x400000>;
> +        clock-names = "dram_core", "dram_pll", "dram_alt", "dram_apb";
> +        clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
> +                 <&clk IMX8MM_DRAM_PLL>,
> +                 <&clk IMX8MM_CLK_DRAM_ALT>,
> +                 <&clk IMX8MM_CLK_DRAM_APB>;
> +        operating-points-v2 = <&ddrc_opp_table>;
> +    };
> -- 
> 2.17.1
>
Leonard Crestez Nov. 5, 2019, 7:25 p.m. UTC | #2
On 05.11.2019 00:21, Rob Herring wrote:
> On Thu, Oct 31, 2019 at 11:50:24PM +0200, Leonard Crestez wrote:
>> Add devicetree bindings for the i.MX DDR Controller on imx8m series
>> chips. It supports dynamic frequency switching between multiple data
>> rates and this is exposed to Linux via the devfreq subsystem.
>>
>> Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
>> ---
>>   .../devicetree/bindings/devfreq/imx-ddrc.yaml | 60 +++++++++++++++++++
> 
> .../bindings/memory-controllers/

Okay, but I'm not sure about the rules here. Usually there is a 1:1 
mapping between subsystems and bindings directory but I guess devfreq is 
odd since it's not really a physical class of device.

I saw there is also a drivers/memory and there is already a 
devfreq-using driver in there (EXYNOS5422_DMC).

It's not clear if my driver fits in there; as far as I can see the only 
"core" functionality in drivers/memory is parsing DDR timings from DTS 
but for imx8m this is all controlled in firmware.

>>   1 file changed, 60 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/devfreq/imx-ddrc.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/devfreq/imx-ddrc.yaml b/Documentation/devicetree/bindings/devfreq/imx-ddrc.yaml
>> new file mode 100644
>> index 000000000000..31db204e6845
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/devfreq/imx-ddrc.yaml
>> @@ -0,0 +1,60 @@
>> +# SPDX-License-Identifier: GPL-2.0
> 
> For new bindings:
> 
> # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> 
>> +%YAML 1.2
>> +---
>> +$id: https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fschemas%2Fdevfreq%2Fimx-devfreq.yaml%23&amp;data=02%7C01%7Cleonard.crestez%40nxp.com%7Cba47e72161764d5a969a08d761755736%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C637085028918247356&amp;sdata=2DjKgyATOPu7qhzpOCfRrmUM0%2FSAQrV9R7AxZxib8gk%3D&amp;reserved=0
> 
> Run 'make dt_binding_check'. This will fail as the filename doesn't
> match.
> 
>> +$schema: https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fmeta-schemas%2Fcore.yaml%23&amp;data=02%7C01%7Cleonard.crestez%40nxp.com%7Cba47e72161764d5a969a08d761755736%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C637085028918247356&amp;sdata=EbyVK2ZF6Z22vE%2F4LfIVv0S1LoMe7%2BxhM43H1i8nxtE%3D&amp;reserved=0
>> +
>> +title: i.MX DDR Controller
> 
> Perhaps i.MX8x as it's not all i.MX chips. And the filename too?

Ok, will rename to imx8m-ddrc since it's not even for all imx8.

>> +
>> +maintainers:
>> +  - Leonard Crestez <leonard.crestez@nxp.com>
>> +
>> +properties:
>> +  compatible:
>> +    items:
>> +      - enum:
>> +        - fsl,imx8mn-ddrc
>> +        - fsl,imx8mm-ddrc
>> +        - fsl,imx8mq-ddrc
>> +      - const: fsl,imx8m-ddrc
>> +
>> +  reg:
>> +    maxItems: 1
>> +
>> +  clocks:
>> +    maxItems: 4
>> +
>> +  clock-names:
>> +    items:
>> +      - const: dram_core
>> +      - const: dram_pll
>> +      - const: dram_alt
>> +      - const: dram_apb
> 
> Drop 'dram_'

OK

>> +
>> +  operating-points-v2: true
>> +
>> +  devfreq-events:
>> +    description: Phandle of PMU node
>> +    $ref: "/schemas/types.yaml#/definitions/phandle"
>> +
>> +required:
>> +  - reg
>> +  - compatible
>> +  - clocks
>> +  - clock-names
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> +  - |
>> +    #include <dt-bindings/clock/imx8mm-clock.h>
>> +    ddrc: dram-controller@3d400000 {
>> +        compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
>> +        reg = <0x3d400000 0x400000>;
>> +        clock-names = "dram_core", "dram_pll", "dram_alt", "dram_apb";
>> +        clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
>> +                 <&clk IMX8MM_DRAM_PLL>,
>> +                 <&clk IMX8MM_CLK_DRAM_ALT>,
>> +                 <&clk IMX8MM_CLK_DRAM_APB>;
>> +        operating-points-v2 = <&ddrc_opp_table>;
>> +    };
Rob Herring (Arm) Nov. 5, 2019, 8:13 p.m. UTC | #3
On Tue, Nov 05, 2019 at 07:25:57PM +0000, Leonard Crestez wrote:
> On 05.11.2019 00:21, Rob Herring wrote:
> > On Thu, Oct 31, 2019 at 11:50:24PM +0200, Leonard Crestez wrote:
> >> Add devicetree bindings for the i.MX DDR Controller on imx8m series
> >> chips. It supports dynamic frequency switching between multiple data
> >> rates and this is exposed to Linux via the devfreq subsystem.
> >>
> >> Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
> >> ---
> >>   .../devicetree/bindings/devfreq/imx-ddrc.yaml | 60 +++++++++++++++++++
> > 
> > .../bindings/memory-controllers/
> 
> Okay, but I'm not sure about the rules here. Usually there is a 1:1 
> mapping between subsystems and bindings directory but I guess devfreq is 
> odd since it's not really a physical class of device.

Mostly true, but it's not completely 1:1.


> I saw there is also a drivers/memory and there is already a 
> devfreq-using driver in there (EXYNOS5422_DMC).

Yeah, well it's been a while since I last tried to clean up locations of 
things. DDR controller bindings are not in the best shape.


> It's not clear if my driver fits in there; as far as I can see the only 
> "core" functionality in drivers/memory is parsing DDR timings from DTS 
> but for imx8m this is all controlled in firmware.

You shouldn't have to think about that. Bindings should be for DDR 
controllers regardless of whether there's a driver for devfreq, EDAC, 
perf, or ??? or all of those.

Rob
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/devfreq/imx-ddrc.yaml b/Documentation/devicetree/bindings/devfreq/imx-ddrc.yaml
new file mode 100644
index 000000000000..31db204e6845
--- /dev/null
+++ b/Documentation/devicetree/bindings/devfreq/imx-ddrc.yaml
@@ -0,0 +1,60 @@ 
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/devfreq/imx-devfreq.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: i.MX DDR Controller
+
+maintainers:
+  - Leonard Crestez <leonard.crestez@nxp.com>
+
+properties:
+  compatible:
+    items:
+      - enum:
+        - fsl,imx8mn-ddrc
+        - fsl,imx8mm-ddrc
+        - fsl,imx8mq-ddrc
+      - const: fsl,imx8m-ddrc
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 4
+
+  clock-names:
+    items:
+      - const: dram_core
+      - const: dram_pll
+      - const: dram_alt
+      - const: dram_apb
+
+  operating-points-v2: true
+
+  devfreq-events:
+    description: Phandle of PMU node
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+
+required:
+  - reg
+  - compatible
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/imx8mm-clock.h>
+    ddrc: dram-controller@3d400000 {
+        compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
+        reg = <0x3d400000 0x400000>;
+        clock-names = "dram_core", "dram_pll", "dram_alt", "dram_apb";
+        clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
+                 <&clk IMX8MM_DRAM_PLL>,
+                 <&clk IMX8MM_CLK_DRAM_ALT>,
+                 <&clk IMX8MM_CLK_DRAM_APB>;
+        operating-points-v2 = <&ddrc_opp_table>;
+    };