From patchwork Sun Dec 3 11:11:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Baruch Siach X-Patchwork-Id: 10089209 X-Patchwork-Delegate: eduardo.valentin@ti.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id ED4AE6035E for ; Sun, 3 Dec 2017 11:19:01 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D8D8C2904D for ; Sun, 3 Dec 2017 11:19:01 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CDA1E290DC; Sun, 3 Dec 2017 11:19:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A47E32904D for ; Sun, 3 Dec 2017 11:18:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751598AbdLCLSy (ORCPT ); Sun, 3 Dec 2017 06:18:54 -0500 Received: from guitar.tcltek.co.il ([192.115.133.116]:57348 "EHLO mx.tkos.co.il" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751108AbdLCLSx (ORCPT ); Sun, 3 Dec 2017 06:18:53 -0500 Received: from sapphire.lan (unknown [10.0.4.3]) by mx.tkos.co.il (Postfix) with ESMTPA id 1C18F4409BF; Sun, 3 Dec 2017 13:18:51 +0200 (IST) From: Baruch Siach To: Zhang Rui , Eduardo Valentin Cc: devicetree@vger.kernel.org, Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Russell King , Miquel Raynal , linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Baruch Siach Subject: [PATCH v2 3/4] thermal: armada: add support for CP110 Date: Sun, 3 Dec 2017 13:11:23 +0200 Message-Id: X-Mailer: git-send-email 2.15.0 In-Reply-To: References: Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The CP110 component is integrated in the Armada 8k and 7k lines of processors. This patch also adds an option of offset to the MSB of the control register. The existing DT binding for Armada 38x refers to a single 32 bit control register. It turns out that this is actually only the MSB of the control area. Changing the binding to fix that would break existing DT files, so the Armada 38x binding is left as is. The new CP110 binding increases the size of the control area to 64 bits, thus moving the MSB to offset 4. Signed-off-by: Baruch Siach --- v2: No change --- drivers/thermal/armada_thermal.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/thermal/armada_thermal.c b/drivers/thermal/armada_thermal.c index 0eb82097571f..59b75f63945d 100644 --- a/drivers/thermal/armada_thermal.c +++ b/drivers/thermal/armada_thermal.c @@ -73,6 +73,7 @@ struct armada_thermal_data { unsigned int temp_shift; unsigned int temp_mask; unsigned int is_valid_shift; + unsigned int control_msb_offset; }; static void armadaxp_init_sensor(struct platform_device *pdev, @@ -142,12 +143,14 @@ static void armada375_init_sensor(struct platform_device *pdev, static void armada380_init_sensor(struct platform_device *pdev, struct armada_thermal_priv *priv) { - unsigned long reg = readl_relaxed(priv->control); + void __iomem *control_msb = + priv->control + priv->data->control_msb_offset; + unsigned long reg = readl_relaxed(control_msb); /* Reset hardware once */ if (!(reg & A380_HW_RESET)) { reg |= A380_HW_RESET; - writel(reg, priv->control); + writel(reg, control_msb); mdelay(10); } } @@ -266,6 +269,19 @@ static const struct armada_thermal_data armada_ap806_data = { .signed_sample = true, }; +static const struct armada_thermal_data armada_cp110_data = { + .is_valid = armada_is_valid, + .init_sensor = armada380_init_sensor, + .is_valid_shift = 10, + .temp_shift = 0, + .temp_mask = 0x3ff, + .control_msb_offset = 4, + .coef_b = 1172499100UL, + .coef_m = 2000096UL, + .coef_div = 4201, + .inverted = true, +}; + static const struct of_device_id armada_thermal_id_table[] = { { .compatible = "marvell,armadaxp-thermal", @@ -287,6 +303,10 @@ static const struct of_device_id armada_thermal_id_table[] = { .compatible = "marvell,armada-ap806-thermal", .data = &armada_ap806_data, }, + { + .compatible = "marvell,armada-cp110-thermal", + .data = &armada_cp110_data, + }, { /* sentinel */ },