@@ -227,7 +227,7 @@ static void amd_pstate_ut_check_freq(u32 index)
goto skip_test;
}
- if (cpudata->boost_supported) {
+ if (amd_pstate_global_params.cpb_boost) {
if ((policy->max == cpudata->max_freq) ||
(policy->max == cpudata->nominal_freq))
amd_pstate_ut_cases[index].result = AMD_PSTATE_UT_RESULT_PASS;
@@ -97,6 +97,7 @@ static struct quirk_entry *quirks;
/* export the amd_pstate_global_params for unit test */
struct amd_pstate_global_params amd_pstate_global_params;
EXPORT_SYMBOL_GPL(amd_pstate_global_params);
+static int amd_pstate_cpu_boost(int cpu, bool state);
/*
* AMD Energy Preference Performance (EPP)
@@ -139,6 +140,16 @@ static unsigned int epp_values[] = {
[EPP_INDEX_POWERSAVE] = AMD_CPPC_EPP_POWERSAVE,
};
+enum CPB_STATE_INDEX {
+ CPB_STATE_DISABLED = 0,
+ CPB_STATE_ENABLED = 1,
+};
+
+static const char * const cpb_state[] = {
+ [CPB_STATE_DISABLED] = "disabled",
+ [CPB_STATE_ENABLED] = "enabled",
+};
+
typedef int (*cppc_mode_transition_fn)(int);
static struct quirk_entry quirk_amd_7k62 = {
@@ -734,6 +745,7 @@ static int amd_pstate_init_boost_support(struct amd_cpudata *cpudata)
if (amd_pstate_global_params.cpb_supported) {
current_pstate_driver->boost_enabled = true;
cpudata->boost_supported = true;
+ cpudata->boost_state = true;
}
amd_pstate_global_params.cpb_boost = amd_pstate_global_params.cpb_supported;
@@ -741,6 +753,7 @@ static int amd_pstate_init_boost_support(struct amd_cpudata *cpudata)
exit_err:
cpudata->boost_supported = false;
+ cpudata->boost_state = false;
current_pstate_driver->boost_enabled = false;
amd_pstate_global_params.cpb_boost = false;
return ret;
@@ -1352,6 +1365,118 @@ static ssize_t prefcore_show(struct device *dev,
return sysfs_emit(buf, "%s\n", str_enabled_disabled(amd_pstate_prefcore));
}
+static int amd_pstate_cpu_boost_update(struct cpufreq_policy *policy, bool on)
+{
+ struct amd_cpudata *cpudata = policy->driver_data;
+ struct cppc_perf_ctrls perf_ctrls;
+ u32 highest_perf, nominal_perf, nominal_freq, max_freq;
+ int ret;
+
+ highest_perf = READ_ONCE(cpudata->highest_perf);
+ nominal_perf = READ_ONCE(cpudata->nominal_perf);
+ nominal_freq = READ_ONCE(cpudata->nominal_freq);
+ max_freq = READ_ONCE(cpudata->max_freq);
+
+ if (boot_cpu_has(X86_FEATURE_CPPC)) {
+ u64 value = READ_ONCE(cpudata->cppc_req_cached);
+
+ value &= ~GENMASK_ULL(7, 0);
+ value |= on ? highest_perf : nominal_perf;
+ WRITE_ONCE(cpudata->cppc_req_cached, value);
+
+ wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);
+ } else {
+ perf_ctrls.max_perf = on ? highest_perf : nominal_perf;
+ ret = cppc_set_perf(cpudata->cpu, &perf_ctrls);
+ if (ret) {
+ cpufreq_cpu_release(policy);
+ pr_debug("Failed to set max perf on CPU:%d. ret:%d\n",
+ cpudata->cpu, ret);
+ return ret;
+ }
+ }
+
+ if (on)
+ policy->cpuinfo.max_freq = max_freq;
+ else
+ policy->cpuinfo.max_freq = nominal_freq * 1000;
+
+ policy->max = policy->cpuinfo.max_freq;
+
+ if (cppc_state == AMD_PSTATE_PASSIVE) {
+ ret = freq_qos_update_request(&cpudata->req[1], policy->cpuinfo.max_freq);
+ if (ret < 0)
+ pr_debug("Failed to update freq constraint: CPU%d\n", cpudata->cpu);
+ }
+
+ return ret < 0 ? ret : 0;
+}
+
+static int amd_pstate_cpu_boost(int cpu, bool state)
+{
+ int ret;
+ struct cpufreq_policy *policy = cpufreq_cpu_get(cpu);
+ struct amd_cpudata *cpudata = policy->driver_data;
+
+ if (!policy) {
+ pr_err("policy is NULL\n");
+ ret = -ENODATA;
+ goto err_exit;
+ }
+
+ ret = amd_pstate_cpu_boost_update(policy, state);
+ refresh_frequency_limits(policy);
+ WRITE_ONCE(cpudata->boost_state, state);
+ policy->boost_enabled = state;
+
+err_exit:
+ cpufreq_cpu_put(policy);
+ return ret < 0 ? ret : 0;
+}
+
+static ssize_t cpb_boost_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ bool cpb_idx;
+
+ cpb_idx = amd_pstate_global_params.cpb_boost;
+
+ return sysfs_emit(buf, "%s\n", cpb_state[cpb_idx]);
+}
+
+static ssize_t cpb_boost_store(struct device *dev, struct device_attribute *b,
+ const char *buf, size_t count)
+{
+ bool new_state;
+ ssize_t ret;
+ int cpu, cpb_idx;
+
+ if (!amd_pstate_global_params.cpb_supported) {
+ pr_err("Boost mode is not supported by this processor or SBIOS\n");
+ return -EINVAL;
+ }
+
+ cpb_idx = sysfs_match_string(cpb_state, buf);
+ if (cpb_idx < 0)
+ return -EINVAL;
+
+ new_state = cpb_idx;
+
+ mutex_lock(&amd_pstate_driver_lock);
+ for_each_present_cpu(cpu) {
+ ret = amd_pstate_cpu_boost(cpu, new_state);
+ if (ret < 0) {
+ pr_warn("failed to update cpu boost for CPU%d (%zd)\n", cpu, ret);
+ goto err_exit;
+ }
+ }
+ amd_pstate_global_params.cpb_boost = !!new_state;
+
+err_exit:
+ mutex_unlock(&amd_pstate_driver_lock);
+ return ret < 0 ? ret : count;
+}
+
cpufreq_freq_attr_ro(amd_pstate_max_freq);
cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq);
@@ -1362,6 +1487,7 @@ cpufreq_freq_attr_rw(energy_performance_preference);
cpufreq_freq_attr_ro(energy_performance_available_preferences);
static DEVICE_ATTR_RW(status);
static DEVICE_ATTR_RO(prefcore);
+static DEVICE_ATTR_RW(cpb_boost);
static struct freq_attr *amd_pstate_attr[] = {
&amd_pstate_max_freq,
@@ -1386,6 +1512,7 @@ static struct freq_attr *amd_pstate_epp_attr[] = {
static struct attribute *pstate_global_attributes[] = {
&dev_attr_status.attr,
&dev_attr_prefcore.attr,
+ &dev_attr_cpb_boost.attr,
NULL
};
@@ -1424,7 +1551,7 @@ static int amd_pstate_init_boost(struct cpufreq_policy *policy)
if (ret)
return ret;
- policy->boost_enabled = READ_ONCE(cpudata->boost_supported);
+ policy->boost_enabled = READ_ONCE(cpudata->boost_state);
return 0;
}
@@ -100,6 +100,7 @@ struct amd_cpudata {
u64 cppc_cap1_cached;
bool suspended;
s16 epp_default;
+ bool boost_state;
};
/**