From patchwork Tue Apr 17 09:07:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: yuankuiz@codeaurora.org X-Patchwork-Id: 10344607 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 662D060542 for ; Tue, 17 Apr 2018 09:07:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5C06828A0D for ; Tue, 17 Apr 2018 09:07:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4FDB728A14; Tue, 17 Apr 2018 09:07:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DF31628A22 for ; Tue, 17 Apr 2018 09:07:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752250AbeDQJHb (ORCPT ); Tue, 17 Apr 2018 05:07:31 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:38884 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751238AbeDQJHa (ORCPT ); Tue, 17 Apr 2018 05:07:30 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 7634F6090E; Tue, 17 Apr 2018 09:07:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1523956049; bh=p1JAOXFv0UUPD7zV+uszOoM3u3EYf2erkll1qfbPFWg=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=etZ23uXMYrTIQIQMMW51s2DttQjhBme/thTm0j0Gwjoj9szrK0Ao88wlF8i/f4GV0 HSBDpELIQ9IWZVlEHcEWkJDFtLg5E97RpDaoC1NXpSjul5qHAc7RARPaXPPakLqkE+ RGllckVeh9plEcOZ4ioG7yq4UJjpWp3g8j4kcKs8= Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id 15040606AC; Tue, 17 Apr 2018 09:07:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1523956048; bh=p1JAOXFv0UUPD7zV+uszOoM3u3EYf2erkll1qfbPFWg=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=B0D3dgCY1ahTdrTaE1DV1UVuj/H/fuJ44YchrEq2dDr8XJg2l7hpM4WnhuE3inJOR JFMzewLCJR+Ienk3NkJi5wA++n9zEqlBuB1JnSJUd8mvvGuu4RcxkLLYGXSjgSjSbi cFKhuUvMvT8T5pKWRMLNZFmyUv97GXeFwGY+VRyQ= MIME-Version: 1.0 Date: Tue, 17 Apr 2018 17:07:28 +0800 From: yuankuiz@codeaurora.org To: Julia Lawall Cc: Joe Perches , Andrew Morton , Peter Zijlstra , "Rafael J. Wysocki" , Andy Whitcroft , Linux PM , "Rafael J. Wysocki" , Frederic Weisbecker , Thomas Gleixner , paulmck@linux.vnet.ibm.com, Ingo Molnar , Len Brown , Linux Kernel Mailing List , linux-pm-owner@vger.kernel.org Subject: Re: [PATCH] checkpatch: Add a --strict test for structs with bool member definitions In-Reply-To: References: <891d4f632fbff5052e11f2d0b6fac35d@codeaurora.org> <20180410123305.GF4082@hirez.programming.kicks-ass.net> <95477c93db187bab6da8a8ba7c57836868446179.camel@perches.com> <20180410143950.4b8526073b4e3e34689f68cb@linux-foundation.org> <20180410150011.df9e036f57b5bcac7ac19686@linux-foundation.org> <20180411081502.GJ4082@hirez.programming.kicks-ass.net> <20180411092959.e666ec443e4d3bb6f43901d7@linux-foundation.org> <1c9f185f6086e9d89659f93720a27b660ee17c13.camel@perches.com> Message-ID: X-Sender: yuankuiz@codeaurora.org User-Agent: Roundcube Webmail/1.2.5 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Hi julia, On 2018-04-15 05:19 AM, Julia Lawall wrote: > On Wed, 11 Apr 2018, Joe Perches wrote: > >> On Thu, 2018-04-12 at 08:22 +0200, Julia Lawall wrote: >> > On Wed, 11 Apr 2018, Joe Perches wrote: >> > > On Wed, 2018-04-11 at 09:29 -0700, Andrew Morton wrote: >> > > > We already have some 500 bools-in-structs >> > > >> > > I got at least triple that only in include/ >> > > so I expect there are at probably an order >> > > of magnitude more than 500 in the kernel. >> > > >> > > I suppose some cocci script could count the >> > > actual number of instances. A regex can not. >> > >> > I got 12667. >> >> Could you please post the cocci script? >> >> > I'm not sure to understand the issue. Will using a bitfield help if there >> > are no other bitfields in the structure? >> >> IMO, not really. >> >> The primary issue is described by Linus here: >> https://lkml.org/lkml/2017/11/21/384 >> >> I personally do not find a significant issue with >> uncontrolled sizes of bool in kernel structs as >> all of the kernel structs are transitory and not >> written out to storage. >> >> I suppose bool bitfields are also OK, but for the >> RMW required. >> >> Using unsigned int :1 bitfield instead of bool :1 >> has the negative of truncation so that the uint >> has to be set with !! instead of a simple assign. > > At least with gcc 5.4.0, a number of structures become larger with > unsigned int :1. bool:1 seems to mostly solve this problem. The > structure > ichx_desc, defined in drivers/gpio/gpio-ich.c seems to become larger > with > both approaches. [ZJ] Hopefully, this could make it better in your environment. IMHO, this is just for double check. uint ngpio; @@ -77,24 +89,12 @@ struct ichx_desc { const u8 (*regs)[3]; const u8 *reglen; - /* GPO_BLINK is available on this chipset */ - bool have_blink; - - /* Whether the chipset has GPIO in GPE0_STS in the PM IO region */ - bool uses_gpe0; - /* USE_SEL is bogus on some chipsets, eg 3100 */ u32 use_sel_ignore[3]; /* Some chipsets have quirks, let these use their own request/get */ int (*request)(struct gpio_chip *chip, unsigned offset); int (*get)(struct gpio_chip *chip, unsigned offset); - - /* - * Some chipsets don't let reading output values on GPIO_LVL register - * this option allows driver caching written output values - */ - bool use_outlvl_cache; }; ZJ diff --git a/drivers/gpio/gpio-ich.c b/drivers/gpio/gpio-ich.c index 4f6d643..b46e170 100644 --- a/drivers/gpio/gpio-ich.c +++ b/drivers/gpio/gpio-ich.c @@ -70,6 +70,18 @@ static const u8 avoton_reglen[3] = { #define ICHX_READ(reg, base_res) inl((reg) + (base_res)->start) struct ichx_desc { + /* GPO_BLINK is available on this chipset */ + bool uses_gpe0:1; + + /* Whether the chipset has GPIO in GPE0_STS in the PM IO region */ + bool uses_gpe0:1; + + /* + * Some chipsets don't let reading output values on GPIO_LVL register + * this option allows driver caching written output values + */ + bool use_outlvl_cache:1; + /* Max GPIO pins the chipset can have */