From patchwork Fri Feb 1 04:11:36 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Len Brown X-Patchwork-Id: 2076441 X-Patchwork-Delegate: lenb@kernel.org Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 521C8DFE75 for ; Fri, 1 Feb 2013 04:12:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751582Ab3BAELy (ORCPT ); Thu, 31 Jan 2013 23:11:54 -0500 Received: from mail-vb0-f52.google.com ([209.85.212.52]:35136 "EHLO mail-vb0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754769Ab3BAELv (ORCPT ); Thu, 31 Jan 2013 23:11:51 -0500 Received: by mail-vb0-f52.google.com with SMTP id fa15so2195083vbb.39 for ; Thu, 31 Jan 2013 20:11:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:in-reply-to:references:reply-to:organization; bh=94d0SoalOu0WnhCafpBoLXFx+3FL1hNAGKEah0hmTO4=; b=z34bCRgECvbOZHAoz2Hw+B9gIAeKuY0EO4I+U5sDiSp7uLIJPTtwZn8FNvdFqgqg96 bKQzTAAm/sijrko2BVS6/45bgP+8Zcps5uvu69ueeTPJPHMtCjzo9q2a3hbZfpMiVGwf cL8gQn7XSIo6U4u0TU3mXMgk/la1nNY+jgf5D6Oadgl9W/d5mlNCAXPJhPevyE9a5vUM s55s42wZOgea/4dgX28CwR0t7ugsKEXXsvQN7XKXtAPSjlRZ7ic6WBGpC0uBNVE7YLyR MjA1tvZVDwY0Y9+CJ0XEOptbweHsCcamXNsPk4ElnuPoioJ2n0Xbc8jKQEJj9c40rNmw wcgg== X-Received: by 10.220.40.135 with SMTP id k7mr10111320vce.12.1359691910992; Thu, 31 Jan 2013 20:11:50 -0800 (PST) Received: from x980.localdomain6 (pool-108-7-58-246.bstnma.fios.verizon.net. [108.7.58.246]) by mx.google.com with ESMTPS id cl9sm7079625vdb.3.2013.01.31.20.11.47 (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 31 Jan 2013 20:11:50 -0800 (PST) From: Len Brown To: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Len Brown Subject: [PATCH 4/4] intel_idle: initial HSW support Date: Thu, 31 Jan 2013 23:11:36 -0500 Message-Id: X-Mailer: git-send-email 1.8.1.2.422.g08c0e7f In-Reply-To: <1359691896-23567-1-git-send-email-lenb@kernel.org> References: <1359691896-23567-1-git-send-email-lenb@kernel.org> In-Reply-To: <9a38405338d7464c852c4524465f84f8a2ac22fb.1359691799.git.len.brown@intel.com> References: <9a38405338d7464c852c4524465f84f8a2ac22fb.1359691799.git.len.brown@intel.com> Reply-To: Len Brown Organization: Intel Open Source Technology Center Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Len Brown This patch enables intel_idle to run on the next-generation Intel(R) Microarchitecture code named Haswell. Signed-off-by: Len Brown --- drivers/idle/intel_idle.c | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c index 8331753..85d50a1 100644 --- a/drivers/idle/intel_idle.c +++ b/drivers/idle/intel_idle.c @@ -212,6 +212,38 @@ static struct cpuidle_state ivb_cstates[MWAIT_MAX_NUM_CSTATES] = { .enter = &intel_idle }, }; +static struct cpuidle_state hsw_cstates[MWAIT_MAX_NUM_CSTATES] = { + { /* MWAIT C0 */ }, + { /* MWAIT C1 */ + .name = "C1-HSW", + .desc = "MWAIT 0x00", + .flags = MWAIT_EAX_2_flags(0x00) | CPUIDLE_FLAG_TIME_VALID, + .exit_latency = 2, + .target_residency = 2, + .enter = &intel_idle }, + { /* MWAIT C2 */ + .name = "C3-HSW", + .desc = "MWAIT 0x10", + .flags = MWAIT_EAX_2_flags(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, + .exit_latency = 39, + .target_residency = 117, + .enter = &intel_idle }, + { /* MWAIT C3 */ + .name = "C6-HSW", + .desc = "MWAIT 0x20", + .flags = MWAIT_EAX_2_flags(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, + .exit_latency = 55, + .target_residency = 165, + .enter = &intel_idle }, + { /* MWAIT C4 */ + .name = "C7-HSW", + .desc = "MWAIT 0x30", + .flags = MWAIT_EAX_2_flags(0x32) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, + .exit_latency = 79, + .target_residency = 237, + .enter = &intel_idle }, +}; + static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = { { /* MWAIT C0 */ }, { /* MWAIT C1 */ @@ -365,6 +397,10 @@ static const struct idle_cpu idle_cpu_ivb = { .state_table = ivb_cstates, }; +static const struct idle_cpu idle_cpu_hsw = { + .state_table = hsw_cstates, +}; + #define ICPU(model, cpu) \ { X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu } @@ -382,6 +418,9 @@ static const struct x86_cpu_id intel_idle_ids[] = { ICPU(0x2d, idle_cpu_snb), ICPU(0x3a, idle_cpu_ivb), ICPU(0x3e, idle_cpu_ivb), + ICPU(0x3c, idle_cpu_hsw), + ICPU(0x3f, idle_cpu_hsw), + ICPU(0x45, idle_cpu_hsw), {} }; MODULE_DEVICE_TABLE(x86cpu, intel_idle_ids);