From patchwork Thu May 28 07:29:56 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 6496471 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 8C2C6C0020 for ; Thu, 28 May 2015 07:30:18 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9A48920630 for ; Thu, 28 May 2015 07:30:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9C31720629 for ; Thu, 28 May 2015 07:30:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752776AbbE1HaP (ORCPT ); Thu, 28 May 2015 03:30:15 -0400 Received: from mail-pa0-f47.google.com ([209.85.220.47]:33271 "EHLO mail-pa0-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753272AbbE1HaO (ORCPT ); Thu, 28 May 2015 03:30:14 -0400 Received: by padbw4 with SMTP id bw4so17235411pad.0 for ; Thu, 28 May 2015 00:30:14 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=zKam8fzvYnjwWp3hQGvZFNbzTJ2MLJ/71UVmN9eQ/Qc=; b=faSrdWSrknVCw8qOzqxhYt5XiLv7xGP8orPnizrbkyP+FudApMyj8t/IAFIawC7E2V 7osNzMlDvS1pqDHZntQpXGz80GA1tlsFWsfPnBRVrOYLJiignqgplYR82bqOFTUqmWvR dD4kj8VzKnXOjEqS+yWJmDPNPwRbKbZOqHtOE6Zcbvs6lxOOtVIXxrX6ox1yRqiC3BlE iKL8yCfhxNJ364Qfx7BTwjjNC+MQv9pBCPl8MtB2XutjqrnaSavL/1quJUXcaQ24gokl ElEsmMPQnfrlml8RXpjBvLsWFKSYT2o+JIHw49XfsNaw0kh6+lORbtCyikzYuuQojAgZ CWvg== X-Gm-Message-State: ALoCoQnGqqypKDClIXvl/egilog5CKENkunpOuW19bHYG3NVWZfrkCgeoTemt84NJkLIE2v9UeKP X-Received: by 10.66.168.105 with SMTP id zv9mr2884375pab.121.1432798213954; Thu, 28 May 2015 00:30:13 -0700 (PDT) Received: from localhost ([122.167.219.251]) by mx.google.com with ESMTPSA id cp10sm1336701pdb.44.2015.05.28.00.30.12 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 28 May 2015 00:30:13 -0700 (PDT) From: Viresh Kumar To: Rafael Wysocki , rob.herring@linaro.org Cc: linaro-kernel@lists.linaro.org, linux-pm@vger.kernel.org, arnd.bergmann@linaro.org, nm@ti.com, broonie@kernel.org, mike.turquette@linaro.org, sboyd@codeaurora.org, grant.likely@linaro.org, olof@lixom.net, Sudeep.Holla@arm.com, devicetree@vger.kernel.org, viswanath.puttagunta@linaro.org, l.stach@pengutronix.de, thomas.petazzoni@free-electrons.com, linux-arm-kernel@lists.infradead.org, ta.omasab@gmail.com, kesavan.abhilash@gmail.com, khilman@linaro.org, santosh.shilimkar@oracle.com, Viresh Kumar Subject: [PATCH V6 2/3] OPP: Allow multiple OPP tables to be passed via DT Date: Thu, 28 May 2015 12:59:56 +0530 Message-Id: X-Mailer: git-send-email 2.4.0 In-Reply-To: References: In-Reply-To: References: Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On some platforms (Like Qualcomm's SoCs), it is not decided until runtime on what OPPs to use. The OPP tables can be fixed at compile time, but which table to use is found out only after reading some efuses (sort of an prom) and knowing characteristics of the SoC. To support such platform we need to pass multiple OPP tables per device and hardware should be able to choose one and only one table out of those. Update OPP-v2 bindings to support that. Acked-by: Nishanth Menon Reviewed-by: Stephen Boyd Signed-off-by: Viresh Kumar --- Documentation/devicetree/bindings/power/opp.txt | 52 +++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/Documentation/devicetree/bindings/power/opp.txt b/Documentation/devicetree/bindings/power/opp.txt index 0ca96e73d2a3..f6f75545149e 100644 --- a/Documentation/devicetree/bindings/power/opp.txt +++ b/Documentation/devicetree/bindings/power/opp.txt @@ -45,6 +45,9 @@ Devices supporting OPPs must set their "operating-points-v2" property with phandle to a OPP table in their DT node. The OPP core will use this phandle to find the operating points for the device. +Devices may want to choose OPP tables at runtime and so can provide a list of +phandles here. But only *one* of them should be chosen at runtime. + If required, this can be extended for SoC vendor specfic bindings. Such bindings should be documented as Documentation/devicetree/bindings/power/-opp.txt and should have a compatible description like: "operating-points-v2-". @@ -63,6 +66,9 @@ This describes the OPPs belonging to a device. This node can have following reference an OPP. Optional properties: +- opp-name: Name of the OPP table, to uniquely identify it if more than one OPP + table is supplied in "operating-points-v2" property of device. + - opp-shared: Indicates that device nodes using this OPP Table Node's phandle switch their DVFS state together, i.e. they share clock/voltage/current lines. Missing property means devices have independent clock/voltage/current lines, @@ -396,3 +402,49 @@ Example 4: Handling multiple regulators }; }; }; + +Example 5: Multiple OPP tables + +/ { + cpus { + cpu@0 { + compatible = "arm,cortex-a7"; + ... + + opp-supply = <&cpu_supply> + operating-points-v2 = <&cpu0_opp_table_slow>, <&cpu0_opp_table_fast>; + }; + }; + + cpu0_opp_table_slow: opp_table_slow { + compatible = "operating-points-v2"; + opp-name = "slow"; + opp-shared; + + opp00 { + opp-hz = <600000000>; + ... + }; + + opp01 { + opp-hz = <800000000>; + ... + }; + }; + + cpu0_opp_table_fast: opp_table_fast { + compatible = "operating-points-v2"; + opp-name = "fast"; + opp-shared; + + opp10 { + opp-hz = <1000000000>; + ... + }; + + opp11 { + opp-hz = <1100000000>; + ... + }; + }; +};