From patchwork Wed Oct 23 06:53:20 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eli Cohen X-Patchwork-Id: 3086221 Return-Path: X-Original-To: patchwork-linux-rdma@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id B74639F2B7 for ; Wed, 23 Oct 2013 06:53:46 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B34AD202E6 for ; Wed, 23 Oct 2013 06:53:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B9C8E202BE for ; Wed, 23 Oct 2013 06:53:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751469Ab3JWGxn (ORCPT ); Wed, 23 Oct 2013 02:53:43 -0400 Received: from mail-ee0-f50.google.com ([74.125.83.50]:51150 "EHLO mail-ee0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751051Ab3JWGxm (ORCPT ); Wed, 23 Oct 2013 02:53:42 -0400 Received: by mail-ee0-f50.google.com with SMTP id l10so152427eei.9 for ; Tue, 22 Oct 2013 23:53:41 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ieeLW1MkspUNhgtRGjX2BbAFOzpf0aHEQP7JXMX9sa4=; b=FR8oiRCjQAIaaFUrMLsldZKbnLmKa3bO0LwGmQKRHfLQ2ZuNqHkNP+J/50el64FBjG Ti30wekGSJF1rSF/UEoXsfucbKA844fP0vBeUP0QOhJPgf/uaLjJhBD93ejMPNgSGqW8 +hn3qenyxW0ZixBxlAC6WmcBMIAQiFx8cGYebTxc3q46t1nO0p8sDv/nsQgquJpwpVIW Kx8u5e/oJ2XnjZFwR/3E2vjek+Do6ybt+eDiHehVvWWMbLwi4h/lEQyy13vT0DoKOsZk FToogqL9L56OvyDVBRblr3MYifO7oo1MTkJuRqe4pt/FaH8KVpnEwrRJW9L0rW0yx5Wk c5nw== X-Gm-Message-State: ALoCoQlNS2boeCKZLc4Xgo3+6JyYLxbDbrpwXIEHLwTVe8AodPT9CpG+Mr+mbhqVvAx3vlpM8FnL X-Received: by 10.14.203.70 with SMTP id e46mr39127eeo.33.1382511221476; Tue, 22 Oct 2013 23:53:41 -0700 (PDT) Received: from localhost (out.voltaire.com. [193.47.165.251]) by mx.google.com with ESMTPSA id h45sm66251064eeg.5.2013.10.22.23.53.40 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 22 Oct 2013 23:53:41 -0700 (PDT) From: Eli Cohen To: roland@kernel.org Cc: linux-rdma@vger.kernel.org, amirv@mellanox.com, ogerlitz@mellanox.com, yevgenyp@mellanox.com, Eli Cohen Subject: [PATCH for-next 8/9] mlx5: Clear reserved area in set_hca_cap Date: Wed, 23 Oct 2013 09:53:20 +0300 Message-Id: <1382511201-7061-9-git-send-email-eli@mellanox.com> X-Mailer: git-send-email 1.8.1.3 In-Reply-To: <1382511201-7061-1-git-send-email-eli@mellanox.com> References: <1382511201-7061-1-git-send-email-eli@mellanox.com> Sender: linux-rdma-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-rdma@vger.kernel.org X-Spam-Status: No, score=-7.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Firmware spec requires reserved fields to be cleared when calling set_hca_cap. Current code queries and copy to the set area, possibly resulting in reserved bits not cleared. This patch copies only writable fields to the set area. Fix also typo - msx => max Signed-off-by: Eli Cohen --- drivers/net/ethernet/mellanox/mlx5/core/main.c | 35 +++++++++++++++++++++++--- include/linux/mlx5/device.h | 9 +++++-- 2 files changed, 39 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/ethernet/mellanox/mlx5/core/main.c index bc0f5fb..40a9f5e 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/main.c @@ -159,6 +159,36 @@ struct mlx5_reg_host_endianess { u8 rsvd[15]; }; + +#define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) + +enum { + MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | + CAP_MASK(MLX5_CAP_OFF_DCT, 1), +}; + +/* selectively copy writable fields clearing any reserved area + */ +static void copy_rw_fields(struct mlx5_hca_cap *to, struct mlx5_hca_cap *from) +{ + u64 v64; + + to->log_max_qp = from->log_max_qp & 0x1f; + to->log_max_ra_req_dc = from->log_max_ra_req_dc & 0x3f; + to->log_max_ra_res_dc = from->log_max_ra_res_dc & 0x3f; + to->log_max_ra_req_qp = from->log_max_ra_req_qp & 0x3f; + to->log_max_ra_res_qp = from->log_max_ra_res_qp & 0x3f; + to->log_max_atomic_size_qp = from->log_max_atomic_size_qp; + to->log_max_atomic_size_dc = from->log_max_atomic_size_dc; + v64 = be64_to_cpu(from->flags) & MLX5_CAP_BITS_RW_MASK; + to->flags = cpu_to_be64(v64); +} + +enum { + HCA_CAP_OPMOD_GET_MAX = 0, + HCA_CAP_OPMOD_GET_CUR = 1, +}; + static int handle_hca_cap(struct mlx5_core_dev *dev) { struct mlx5_cmd_query_hca_cap_mbox_out *query_out = NULL; @@ -180,7 +210,7 @@ static int handle_hca_cap(struct mlx5_core_dev *dev) } query_ctx.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_QUERY_HCA_CAP); - query_ctx.hdr.opmod = cpu_to_be16(0x1); + query_ctx.hdr.opmod = cpu_to_be16(HCA_CAP_OPMOD_GET_CUR); err = mlx5_cmd_exec(dev, &query_ctx, sizeof(query_ctx), query_out, sizeof(*query_out)); if (err) @@ -192,8 +222,7 @@ static int handle_hca_cap(struct mlx5_core_dev *dev) goto query_ex; } - memcpy(&set_ctx->hca_cap, &query_out->hca_cap, - sizeof(set_ctx->hca_cap)); + copy_rw_fields(&set_ctx->hca_cap, &query_out->hca_cap); if (dev->profile->mask & MLX5_PROF_MASK_QP_SIZE) set_ctx->hca_cap.log_max_qp = dev->profile->log_max_qp; diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h index 5eb4e31..3d789f4 100644 --- a/include/linux/mlx5/device.h +++ b/include/linux/mlx5/device.h @@ -230,6 +230,11 @@ enum { MLX5_MAX_PAGE_SHIFT = 31 }; +enum { + MLX5_CAP_OFF_DCT = 41, + MLX5_CAP_OFF_CMDIF_CSUM = 46, +}; + struct mlx5_inbox_hdr { __be16 opcode; u8 rsvd[4]; @@ -319,9 +324,9 @@ struct mlx5_hca_cap { u8 rsvd25[42]; __be16 log_uar_page_sz; u8 rsvd26[28]; - u8 log_msx_atomic_size_qp; + u8 log_max_atomic_size_qp; u8 rsvd27[2]; - u8 log_msx_atomic_size_dc; + u8 log_max_atomic_size_dc; u8 rsvd28[76]; };