From patchwork Mon Oct 26 14:28:28 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ira Weiny X-Patchwork-Id: 7490191 Return-Path: X-Original-To: patchwork-linux-rdma@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 1551A9F37F for ; Mon, 26 Oct 2015 14:29:25 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 23CA520627 for ; Mon, 26 Oct 2015 14:29:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F31EB206F3 for ; Mon, 26 Oct 2015 14:29:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754356AbbJZO3U (ORCPT ); Mon, 26 Oct 2015 10:29:20 -0400 Received: from mga11.intel.com ([192.55.52.93]:58239 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753975AbbJZO3R (ORCPT ); Mon, 26 Oct 2015 10:29:17 -0400 Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga102.fm.intel.com with ESMTP; 26 Oct 2015 07:29:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,201,1444719600"; d="scan'208";a="803243840" Received: from phlsvsds.ph.intel.com ([10.228.195.38]) by orsmga001.jf.intel.com with ESMTP; 26 Oct 2015 07:29:09 -0700 Received: from phlsvsds.ph.intel.com (localhost.localdomain [127.0.0.1]) by phlsvsds.ph.intel.com (8.13.8/8.13.8) with ESMTP id t9QET7vD008072; Mon, 26 Oct 2015 10:29:07 -0400 Received: (from iweiny@localhost) by phlsvsds.ph.intel.com (8.13.8/8.13.8/Submit) id t9QET6nL008068; Mon, 26 Oct 2015 10:29:06 -0400 X-Authentication-Warning: phlsvsds.ph.intel.com: iweiny set sender to ira.weiny@intel.com using -f From: ira.weiny@intel.com To: gregkh@linuxfoundation.org, devel@driverdev.osuosl.org Cc: dledford@redhat.com, linux-rdma@vger.kernel.org, dennis.dalessandro@intel.com, mike.marciniszyn@intel.com, Easwar Hariharan , Ira Weiny Subject: [PATCH v3 02/23] staging/rdma/hfi1: Fix code to reset ASIC CSRs on FLR Date: Mon, 26 Oct 2015 10:28:28 -0400 Message-Id: <1445869729-7507-3-git-send-email-ira.weiny@intel.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1445869729-7507-1-git-send-email-ira.weiny@intel.com> References: <1445869729-7507-1-git-send-email-ira.weiny@intel.com> Sender: linux-rdma-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-rdma@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Easwar Hariharan The ASIC registers were not reset on FLR, and the code to protect the ASIC block against multiple initializations by peer HFIs did not extend to multiple ASICs in a system. This patch addresses this gap. Reviewed-by: Dean Luick Signed-off-by: Easwar Hariharan Signed-off-by: Ira Weiny --- drivers/staging/rdma/hfi1/chip.c | 35 +++++++++++++++-------------------- drivers/staging/rdma/hfi1/firmware.c | 4 ++++ 2 files changed, 19 insertions(+), 20 deletions(-) diff --git a/drivers/staging/rdma/hfi1/chip.c b/drivers/staging/rdma/hfi1/chip.c index 46ebc381a792..9d8aa1d09724 100644 --- a/drivers/staging/rdma/hfi1/chip.c +++ b/drivers/staging/rdma/hfi1/chip.c @@ -9327,8 +9327,6 @@ static void reset_cce_csrs(struct hfi1_devdata *dd) /* set ASIC CSRs to chip reset defaults */ static void reset_asic_csrs(struct hfi1_devdata *dd) { - static DEFINE_MUTEX(asic_mutex); - static int called; int i; /* @@ -9338,15 +9336,8 @@ static void reset_asic_csrs(struct hfi1_devdata *dd) * a known first load do the reset and blocking all others. */ - /* - * These CSRs should only be reset once - the first one here will - * do the work. Use a mutex so that a non-first caller waits until - * the first is finished before it can proceed. - */ - mutex_lock(&asic_mutex); - if (called) - goto done; - called = 1; + if (!(dd->flags & HFI1_DO_INIT_ASIC)) + return; if (dd->icode != ICODE_FPGA_EMULATION) { /* emulation does not have an SBus - leave these alone */ @@ -9366,7 +9357,10 @@ static void reset_asic_csrs(struct hfi1_devdata *dd) for (i = 0; i < ASIC_NUM_SCRATCH; i++) write_csr(dd, ASIC_CFG_SCRATCH + (8 * i), 0); write_csr(dd, ASIC_CFG_MUTEX, 0); /* this will clear it */ + + /* We might want to retain this state across FLR if we ever use it */ write_csr(dd, ASIC_CFG_DRV_STR, 0); + write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0); /* ASIC_STS_THERM read-only */ /* ASIC_CFG_RESET leave alone */ @@ -9413,9 +9407,6 @@ static void reset_asic_csrs(struct hfi1_devdata *dd) /* this also writes a NOP command, clearing paging mode */ write_csr(dd, ASIC_EEP_ADDR_CMD, 0); write_csr(dd, ASIC_EEP_DATA, 0); - -done: - mutex_unlock(&asic_mutex); } /* set MISC CSRs to chip reset defaults */ @@ -9827,6 +9818,7 @@ static void init_chip(struct hfi1_devdata *dd) restore_pci_variables(dd); } + reset_asic_csrs(dd); } else { dd_dev_info(dd, "Resetting CSRs with writes\n"); reset_cce_csrs(dd); @@ -9837,6 +9829,7 @@ static void init_chip(struct hfi1_devdata *dd) } /* clear the DC reset */ write_csr(dd, CCE_DC_CTRL, 0); + /* Set the LED off */ if (is_a0(dd)) setextled(dd, 0); @@ -10332,7 +10325,7 @@ static void asic_should_init(struct hfi1_devdata *dd) } /** - * Allocate an initialize the device structure for the hfi. + * Allocate and initialize the device structure for the hfi. * @dev: the pci_dev for hfi1_ib device * @ent: pci_device_id struct for this dev * @@ -10488,6 +10481,12 @@ struct hfi1_devdata *hfi1_init_dd(struct pci_dev *pdev, else if (dd->rcv_intr_timeout_csr == 0 && rcv_intr_timeout) dd->rcv_intr_timeout_csr = 1; + /* needs to be done before we look for the peer device */ + read_guid(dd); + + /* should this device init the ASIC block? */ + asic_should_init(dd); + /* obtain chip sizes, reset chip CSRs */ init_chip(dd); @@ -10496,11 +10495,6 @@ struct hfi1_devdata *hfi1_init_dd(struct pci_dev *pdev, if (ret) goto bail_cleanup; - /* needs to be done before we look for the peer device */ - read_guid(dd); - - asic_should_init(dd); - /* read in firmware */ ret = hfi1_firmware_init(dd); if (ret) @@ -10715,6 +10709,7 @@ static int thermal_init(struct hfi1_devdata *dd) acquire_hw_mutex(dd); dd_dev_info(dd, "Initializing thermal sensor\n"); + /* Thermal Sensor Initialization */ /* Step 1: Reset the Thermal SBus Receiver */ ret = sbus_request_slow(dd, SBUS_THERMAL, 0x0, diff --git a/drivers/staging/rdma/hfi1/firmware.c b/drivers/staging/rdma/hfi1/firmware.c index 5c2f2ed8f224..15c9cb7a3150 100644 --- a/drivers/staging/rdma/hfi1/firmware.c +++ b/drivers/staging/rdma/hfi1/firmware.c @@ -1614,6 +1614,10 @@ done: */ void read_guid(struct hfi1_devdata *dd) { + /* Take the DC out of reset to get a valid GUID value */ + write_csr(dd, CCE_DC_CTRL, 0); + (void) read_csr(dd, CCE_DC_CTRL); + dd->base_guid = read_csr(dd, DC_DC8051_CFG_LOCAL_GUID); dd_dev_info(dd, "GUID %llx", (unsigned long long)dd->base_guid);