From patchwork Thu Nov 5 02:06:08 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ira Weiny X-Patchwork-Id: 7556671 Return-Path: X-Original-To: patchwork-linux-rdma@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 7FF0CBEEA4 for ; Thu, 5 Nov 2015 02:06:21 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9061E20823 for ; Thu, 5 Nov 2015 02:06:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 40A692082C for ; Thu, 5 Nov 2015 02:06:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756411AbbKECGR (ORCPT ); Wed, 4 Nov 2015 21:06:17 -0500 Received: from mga11.intel.com ([192.55.52.93]:38084 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756201AbbKECGR (ORCPT ); Wed, 4 Nov 2015 21:06:17 -0500 Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP; 04 Nov 2015 18:06:16 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,245,1444719600"; d="scan'208";a="678615807" Received: from phlsvsds.ph.intel.com ([10.228.195.38]) by orsmga003.jf.intel.com with ESMTP; 04 Nov 2015 18:06:15 -0800 Received: from phlsvsds.ph.intel.com (localhost.localdomain [127.0.0.1]) by phlsvsds.ph.intel.com (8.13.8/8.13.8) with ESMTP id tA526Eso021898; Wed, 4 Nov 2015 21:06:14 -0500 Received: (from iweiny@localhost) by phlsvsds.ph.intel.com (8.13.8/8.13.8/Submit) id tA526D3Z021894; Wed, 4 Nov 2015 21:06:13 -0500 X-Authentication-Warning: phlsvsds.ph.intel.com: iweiny set sender to ira.weiny@intel.com using -f From: ira.weiny@intel.com To: gregkh@linuxfoundation.org, devel@driverdev.osuosl.org Cc: dledford@redhat.com, linux-rdma@vger.kernel.org, mike.marciniszyn@intel.com, Dean Luick , Ira Weiny Subject: [PATCH] staging/rdma/hfi1: set Gen3 half-swing for integrated devices Date: Wed, 4 Nov 2015 21:06:08 -0500 Message-Id: <1446689168-21620-1-git-send-email-ira.weiny@intel.com> X-Mailer: git-send-email 1.7.1 Sender: linux-rdma-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-rdma@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Dean Luick Correctly set half-swing for integrated devices. A0 needs all fields set for CcePcieCtrl. B0 and later only need a few fields set. Reviewed-by: Stuart Summers Signed-off-by: Dean Luick Signed-off-by: Ira Weiny --- drivers/staging/rdma/hfi1/chip_registers.h | 11 +++++ drivers/staging/rdma/hfi1/pcie.c | 74 ++++++++++++++++++++++++++++-- 2 files changed, 81 insertions(+), 4 deletions(-) diff --git a/drivers/staging/rdma/hfi1/chip_registers.h b/drivers/staging/rdma/hfi1/chip_registers.h index bf45de29d8bd..d0deb2278635 100644 --- a/drivers/staging/rdma/hfi1/chip_registers.h +++ b/drivers/staging/rdma/hfi1/chip_registers.h @@ -549,6 +549,17 @@ #define CCE_MSIX_TABLE_UPPER (CCE + 0x000000100008) #define CCE_MSIX_TABLE_UPPER_RESETCSR 0x0000000100000000ull #define CCE_MSIX_VEC_CLR_WITHOUT_INT (CCE + 0x000000110400) +#define CCE_PCIE_CTRL (CCE + 0x0000000000C0) +#define CCE_PCIE_CTRL_PCIE_LANE_BUNDLE_MASK 0x3ull +#define CCE_PCIE_CTRL_PCIE_LANE_BUNDLE_SHIFT 0 +#define CCE_PCIE_CTRL_PCIE_LANE_DELAY_MASK 0xFull +#define CCE_PCIE_CTRL_PCIE_LANE_DELAY_SHIFT 2 +#define CCE_PCIE_CTRL_XMT_MARGIN_OVERWRITE_ENABLE_SHIFT 8 +#define CCE_PCIE_CTRL_XMT_MARGIN_SHIFT 9 +#define CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_MASK 0x1ull +#define CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_SHIFT 12 +#define CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_MASK 0x7ull +#define CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_SHIFT 13 #define CCE_REVISION (CCE + 0x000000000000) #define CCE_REVISION2 (CCE + 0x000000000008) #define CCE_REVISION2_HFI_ID_MASK 0x1ull diff --git a/drivers/staging/rdma/hfi1/pcie.c b/drivers/staging/rdma/hfi1/pcie.c index a956044459a2..000f28f4b501 100644 --- a/drivers/staging/rdma/hfi1/pcie.c +++ b/drivers/staging/rdma/hfi1/pcie.c @@ -864,6 +864,75 @@ static void arm_gasket_logic(struct hfi1_devdata *dd) read_csr(dd, ASIC_PCIE_SD_HOST_CMD); } +/* CcePcieCtrl long name helper */ +#define PC(field) (CCE_PCIE_CTRL_##field) + + /* + * Write xmt_margin for full-swing (WFR-B) or half-swing (WFR-C). + */ +static void write_xmt_margin(struct hfi1_devdata *dd, const char *fname) +{ + u64 pcie_ctrl; + u64 xmt_margin; + u64 xmt_margin_oe; + u64 lane_delay; + u64 lane_bundle; + + pcie_ctrl = read_csr(dd, CCE_PCIE_CTRL); + + /* + * For Discrete, use full-swing. + * - PCIe TX defaults to full-swing. + * Leave this register as default. + * For Integrated, use half-swing + * - Copy xmt_margin and xmt_margin_oe + * from Gen1/Gen2 to Gen3. + */ + if (dd->pcidev->device == PCI_DEVICE_ID_INTEL1) { /* integrated */ + /* extract initial fields */ + xmt_margin = (pcie_ctrl >> PC(XMT_MARGIN_GEN1_GEN2_SHIFT)) + & PC(XMT_MARGIN_GEN1_GEN2_MASK); + xmt_margin_oe = + (pcie_ctrl + >> PC(XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_SHIFT)) + & PC(XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_MASK); + lane_delay = (pcie_ctrl >> PC(PCIE_LANE_DELAY_SHIFT)) + & PC(PCIE_LANE_DELAY_MASK); + lane_bundle = (pcie_ctrl >> PC(PCIE_LANE_BUNDLE_SHIFT)) + & PC(PCIE_LANE_BUNDLE_MASK); + + /* + * For A0, EFUSE values are not set. Override with the + * correct values. + */ + if (is_a0(dd)) { + /* + * xmt_margin and OverwiteEnabel should be the + * same for Gen1/Gen2 and Gen3 + */ + xmt_margin = 0x5; + xmt_margin_oe = 0x1; + lane_delay = 0xF; /* Delay 240ns. */ + lane_bundle = 0x0; /* Set to 1 lane. */ + } + + /* overwrite existing values */ + pcie_ctrl = (xmt_margin << PC(XMT_MARGIN_GEN1_GEN2_SHIFT)) + | (xmt_margin_oe << + PC(XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_SHIFT)) + | (xmt_margin << PC(XMT_MARGIN_SHIFT)) + | (xmt_margin_oe << + PC(XMT_MARGIN_OVERWRITE_ENABLE_SHIFT)) + | (lane_delay << PC(PCIE_LANE_DELAY_SHIFT)) + | (lane_bundle << PC(PCIE_LANE_BUNDLE_SHIFT)); + + write_csr(dd, CCE_PCIE_CTRL, pcie_ctrl); + } + + dd_dev_info(dd, "%s: program XMT margin, CcePcieCtrl 0x%llx\n", + fname, pcie_ctrl); +} + /* * Do all the steps needed to transition the PCIe link to Gen3 speed. */ @@ -1072,11 +1141,8 @@ retry: /* * step 5d: program XMT margin - * Right now, leave the default alone. To change, do a - * read-modify-write of: - * CcePcieCtrl.XmtMargin - * CcePcieCtrl.XmitMarginOverwriteEnable */ + write_xmt_margin(dd, __func__); /* step 5e: disable active state power management (ASPM) */ dd_dev_info(dd, "%s: clearing ASPM\n", __func__);