From patchwork Fri Dec 18 04:49:53 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ira Weiny X-Patchwork-Id: 7879951 Return-Path: X-Original-To: patchwork-linux-rdma@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id EC4369F1C2 for ; Fri, 18 Dec 2015 04:50:39 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 479172047B for ; Fri, 18 Dec 2015 04:50:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0478620480 for ; Fri, 18 Dec 2015 04:50:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754024AbbLREue (ORCPT ); Thu, 17 Dec 2015 23:50:34 -0500 Received: from mga09.intel.com ([134.134.136.24]:63709 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933009AbbLREub (ORCPT ); Thu, 17 Dec 2015 23:50:31 -0500 Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP; 17 Dec 2015 20:50:25 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,444,1444719600"; d="scan'208";a="874001956" Received: from phlsvsds.ph.intel.com ([10.228.195.38]) by orsmga002.jf.intel.com with ESMTP; 17 Dec 2015 20:50:24 -0800 Received: from phlsvsds.ph.intel.com (localhost.localdomain [127.0.0.1]) by phlsvsds.ph.intel.com (8.13.8/8.13.8) with ESMTP id tBI4oNkJ014075; Thu, 17 Dec 2015 23:50:23 -0500 Received: (from iweiny@localhost) by phlsvsds.ph.intel.com (8.13.8/8.13.8/Submit) id tBI4oMvc014072; Thu, 17 Dec 2015 23:50:22 -0500 X-Authentication-Warning: phlsvsds.ph.intel.com: iweiny set sender to ira.weiny@intel.com using -f From: ira.weiny@intel.com To: gregkh@linuxfoundation.org, devel@driverdev.osuosl.org Cc: dledford@redhat.com, linux-rdma@vger.kernel.org, Mitko Haralanov Subject: [PATCH v2 03/14] uapi/rdma/hfi/hfi1_user.h: Convert definitions to use BIT() macro Date: Thu, 17 Dec 2015 23:49:53 -0500 Message-Id: <1450414204-13699-4-git-send-email-ira.weiny@intel.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1450414204-13699-1-git-send-email-ira.weiny@intel.com> References: <1450414204-13699-1-git-send-email-ira.weiny@intel.com> Sender: linux-rdma-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-rdma@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Mitko Haralanov Convert bit definitions to use BIT() macro as per checkpatch.pl requirements. Reviewed-by: Ira Weiny Signed-off-by: Mitko Haralanov --- include/uapi/rdma/hfi/hfi1_user.h | 56 +++++++++++++++++++-------------------- 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/include/uapi/rdma/hfi/hfi1_user.h b/include/uapi/rdma/hfi/hfi1_user.h index cf172718e3d5..a65f2fe17660 100644 --- a/include/uapi/rdma/hfi/hfi1_user.h +++ b/include/uapi/rdma/hfi/hfi1_user.h @@ -83,29 +83,29 @@ * driver features. The same set of bits are communicated to user * space. */ -#define HFI1_CAP_DMA_RTAIL (1UL << 0) /* Use DMA'ed RTail value */ -#define HFI1_CAP_SDMA (1UL << 1) /* Enable SDMA support */ -#define HFI1_CAP_SDMA_AHG (1UL << 2) /* Enable SDMA AHG support */ -#define HFI1_CAP_EXTENDED_PSN (1UL << 3) /* Enable Extended PSN support */ -#define HFI1_CAP_HDRSUPP (1UL << 4) /* Enable Header Suppression */ -/* 1UL << 5 unused */ -#define HFI1_CAP_USE_SDMA_HEAD (1UL << 6) /* DMA Hdr Q tail vs. use CSR */ -#define HFI1_CAP_MULTI_PKT_EGR (1UL << 7) /* Enable multi-packet Egr buffs*/ -#define HFI1_CAP_NODROP_RHQ_FULL (1UL << 8) /* Don't drop on Hdr Q full */ -#define HFI1_CAP_NODROP_EGR_FULL (1UL << 9) /* Don't drop on EGR buffs full */ -#define HFI1_CAP_TID_UNMAP (1UL << 10) /* Disable Expected TID caching */ -#define HFI1_CAP_PRINT_UNIMPL (1UL << 11) /* Show for unimplemented feats */ -#define HFI1_CAP_ALLOW_PERM_JKEY (1UL << 12) /* Allow use of permissive JKEY */ -#define HFI1_CAP_NO_INTEGRITY (1UL << 13) /* Enable ctxt integrity checks */ -#define HFI1_CAP_PKEY_CHECK (1UL << 14) /* Enable ctxt PKey checking */ -#define HFI1_CAP_STATIC_RATE_CTRL (1UL << 15) /* Allow PBC.StaticRateControl */ -/* 1UL << 16 unused */ -#define HFI1_CAP_SDMA_HEAD_CHECK (1UL << 17) /* SDMA head checking */ -#define HFI1_CAP_EARLY_CREDIT_RETURN (1UL << 18) /* early credit return */ - -#define HFI1_RCVHDR_ENTSIZE_2 (1UL << 0) -#define HFI1_RCVHDR_ENTSIZE_16 (1UL << 1) -#define HFI1_RCVDHR_ENTSIZE_32 (1UL << 2) +#define HFI1_CAP_DMA_RTAIL BIT(0) /* Use DMA'ed RTail value */ +#define HFI1_CAP_SDMA BIT(1) /* Enable SDMA support */ +#define HFI1_CAP_SDMA_AHG BIT(2) /* Enable SDMA AHG support */ +#define HFI1_CAP_EXTENDED_PSN BIT(3) /* Enable Extended PSN support */ +#define HFI1_CAP_HDRSUPP BIT(4) /* Enable Header Suppression */ +/* BIT(5) unused */ +#define HFI1_CAP_USE_SDMA_HEAD BIT(6) /* DMA Hdr Q tail vs. use CSR */ +#define HFI1_CAP_MULTI_PKT_EGR BIT(7) /* Enable multi-packet Egr buffs*/ +#define HFI1_CAP_NODROP_RHQ_FULL BIT(8) /* Don't drop on Hdr Q full */ +#define HFI1_CAP_NODROP_EGR_FULL BIT(9) /* Don't drop on EGR buffs full */ +#define HFI1_CAP_TID_UNMAP BIT(10) /* Disable Expected TID caching */ +#define HFI1_CAP_PRINT_UNIMPL BIT(11) /* Show for unimplemented feats */ +#define HFI1_CAP_ALLOW_PERM_JKEY BIT(12) /* Allow use of permissive JKEY */ +#define HFI1_CAP_NO_INTEGRITY BIT(13) /* Enable ctxt integrity checks */ +#define HFI1_CAP_PKEY_CHECK BIT(14) /* Enable ctxt PKey checking */ +#define HFI1_CAP_STATIC_RATE_CTRL BIT(15) /* Allow PBC.StaticRateControl */ +/* BIT(16) unused */ +#define HFI1_CAP_SDMA_HEAD_CHECK BIT(17) /* SDMA head checking */ +#define HFI1_CAP_EARLY_CREDIT_RETURN BIT(18) /* early credit return */ + +#define HFI1_RCVHDR_ENTSIZE_2 BIT(0) +#define HFI1_RCVHDR_ENTSIZE_16 BIT(1) +#define HFI1_RCVDHR_ENTSIZE_32 BIT(2) /* * If the unit is specified via open, HFI choice is fixed. If port is @@ -149,11 +149,11 @@ #define _HFI1_EVENT_SL2VL_CHANGE_BIT 4 #define _HFI1_MAX_EVENT_BIT _HFI1_EVENT_SL2VL_CHANGE_BIT -#define HFI1_EVENT_FROZEN (1UL << _HFI1_EVENT_FROZEN_BIT) -#define HFI1_EVENT_LINKDOWN (1UL << _HFI1_EVENT_LINKDOWN_BIT) -#define HFI1_EVENT_LID_CHANGE (1UL << _HFI1_EVENT_LID_CHANGE_BIT) -#define HFI1_EVENT_LMC_CHANGE (1UL << _HFI1_EVENT_LMC_CHANGE_BIT) -#define HFI1_EVENT_SL2VL_CHANGE (1UL << _HFI1_EVENT_SL2VL_CHANGE_BIT) +#define HFI1_EVENT_FROZEN BIT(_HFI1_EVENT_FROZEN_BIT) +#define HFI1_EVENT_LINKDOWN BIT(_HFI1_EVENT_LINKDOWN_BIT) +#define HFI1_EVENT_LID_CHANGE BIT(_HFI1_EVENT_LID_CHANGE_BIT) +#define HFI1_EVENT_LMC_CHANGE BIT(_HFI1_EVENT_LMC_CHANGE_BIT) +#define HFI1_EVENT_SL2VL_CHANGE BIT(_HFI1_EVENT_SL2VL_CHANGE_BIT) /* * These are the status bits readable (in ASCII form, 64bit value)