From patchwork Sat Feb 20 07:47:40 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leon Romanovsky X-Patchwork-Id: 8365791 Return-Path: X-Original-To: patchwork-linux-rdma@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 398439F314 for ; Sat, 20 Feb 2016 07:48:47 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 36E8D2051D for ; Sat, 20 Feb 2016 07:48:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2A80420513 for ; Sat, 20 Feb 2016 07:48:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758116AbcBTHsk (ORCPT ); Sat, 20 Feb 2016 02:48:40 -0500 Received: from mail-wm0-f48.google.com ([74.125.82.48]:33439 "EHLO mail-wm0-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758117AbcBTHs3 (ORCPT ); Sat, 20 Feb 2016 02:48:29 -0500 Received: by mail-wm0-f48.google.com with SMTP id g62so95844047wme.0 for ; Fri, 19 Feb 2016 23:48:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=leon-nu.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hdHmWP6q8dI+wvT/OEu7fshXj1BQ6+P807jweJsb93I=; b=TFc1nrK1wOCda3ZnLNYI1jKSIp17A+29LoP3LYL+FRaVTQDL6vNkO6Nb8+gFN0YOmN lFurFWkOo64Rlu2kjzIHcFwOv32rTnLskmmnw5KvP9ETQXR+SdpvGRxtVP29NmrJvPlt PcSlHvQh0G9nbxc5iTmXYoO3FvmdBMX4D1SUpfT2pPGrR8IpKBUxOgRqqq3pwe0todQL 1bGe2hMTjNb9T2z8VX8+McJNJgspCkjq+Ph8kpp8DpEyRRKhLFHU3ggWilRqooBL3Sw9 AtT71hHPvjQMWx+d+56st3646GrBah7o8UlNu7HWVLNh0bDioQpunIh5lOU8oUek4QjE 0BxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hdHmWP6q8dI+wvT/OEu7fshXj1BQ6+P807jweJsb93I=; b=IhyWFrCEx4j0JX+wEhEvQr1bBEPQMBGCg78/AvLNL8vevZWtA0eS/JGFmhrlDClGx7 nKBr6jOZn/HNkiphpZ0va7x4RDEZYGYX1QpJQCUYbZcvEHJ9oHYzV6ggNyDFw+XytAFk 30k8XlBszMS5Dq6Mq16K91HYhsvBnH1zQ8Ad6wy3P6UPVl1zmA2xX8I0BgbC0J34SGxT vTCfZAxmLwepA37JWkJYExFkR/yYPYXpif7HZeq2GCtAgKDEqLgWUnr/D7OGaUn0ZH8D 1tQBtnZr0a1ZtKrArFgHnvjYHx5zTRXs6BOdNjiFiczYBI3N/ndVFz5ukr0+6akn1/bM aWWA== X-Gm-Message-State: AG10YOR0Bv/44i5+w1MfJQTRxQomUtk2hMy8h8eaPS+BS+tCeVgdbRkpXZVcKFcFqlOMJg== X-Received: by 10.195.12.113 with SMTP id ep17mr16684003wjd.102.1455954508266; Fri, 19 Feb 2016 23:48:28 -0800 (PST) Received: from localhost ([213.57.247.249]) by smtp.gmail.com with ESMTPSA id l132sm10935309wmf.7.2016.02.19.23.48.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 19 Feb 2016 23:48:27 -0800 (PST) From: Leon Romanovsky To: dledford@redhat.com, saeedm@mellanox.com Cc: linux-rdma@vger.kernel.org, Leon Romanovsky , Sagi Grimberg Subject: [PATCH rdma-next 3/8] net/mlx5_core: Introduce offload arithmetic hardware capabilities Date: Sat, 20 Feb 2016 09:47:40 +0200 Message-Id: <1455954465-15141-4-git-send-email-leon@leon.nu> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1455954465-15141-1-git-send-email-leon@leon.nu> References: <1455954465-15141-1-git-send-email-leon@leon.nu> Sender: linux-rdma-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-rdma@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Leon Romanovsky Define the necessary hardware structures for the offload arithmetic capabilities and read/cache them on driver load. Signed-off-by: Sagi Grimberg Signed-off-by: Leon Romanovsky Reviewed-by: Saeed Mahameed Acked-by: Max Gurtovoy --- drivers/net/ethernet/mellanox/mlx5/core/fw.c | 6 ++++++ include/linux/mlx5/device.h | 6 ++++++ include/linux/mlx5/mlx5_ifc.h | 31 +++++++++++++++++++++++++++- 3 files changed, 42 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fw.c b/drivers/net/ethernet/mellanox/mlx5/core/fw.c index fe6dfd8..75c7ae6 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fw.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fw.c @@ -145,6 +145,12 @@ int mlx5_query_hca_caps(struct mlx5_core_dev *dev) return err; } + if (MLX5_CAP_GEN(dev, vector_calc)) { + err = mlx5_core_get_caps(dev, MLX5_CAP_VECTOR_CALC); + if (err) + return err; + } + return 0; } diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h index 987764a..1f2cedf 100644 --- a/include/linux/mlx5/device.h +++ b/include/linux/mlx5/device.h @@ -1196,6 +1196,8 @@ enum mlx5_cap_type { MLX5_CAP_FLOW_TABLE, MLX5_CAP_ESWITCH_FLOW_TABLE, MLX5_CAP_ESWITCH, + MLX5_CAP_RESERVED, + MLX5_CAP_VECTOR_CALC, /* NUM OF CAP Types */ MLX5_CAP_NUM }; @@ -1258,6 +1260,10 @@ enum mlx5_cap_type { #define MLX5_CAP_ODP(mdev, cap)\ MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap) +#define MLX5_CAP_VECTOR_CALC(mdev, cap) \ + MLX5_GET(vector_calc_cap, \ + mdev->hca_caps_cur[MLX5_CAP_VECTOR_CALC], cap) + enum { MLX5_CMD_STAT_OK = 0x0, MLX5_CMD_STAT_INT_ERR = 0x1, diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index 455d9cc..d34ad50 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -617,6 +617,33 @@ struct mlx5_ifc_odp_cap_bits { u8 reserved_at_80[0x720]; }; +struct mlx5_ifc_calc_op { + u8 reserved_at_0[0x10]; + u8 reserved_at_10[0x9]; + u8 op_swap_endianness[0x1]; + u8 op_min[0x1]; + u8 op_xor[0x1]; + u8 op_or[0x1]; + u8 op_and[0x1]; + u8 op_max[0x1]; + u8 op_add[0x1]; +}; + +struct mlx5_ifc_vector_calc_cap_bits { + u8 calc_matrix[0x1]; + u8 reserved_at_1[0x1f]; + u8 reserved_at_20[0x8]; + u8 max_vec_count[0x8]; + u8 reserved_at_30[0xd]; + u8 max_chunk_size[0x3]; + struct mlx5_ifc_calc_op calc0; + struct mlx5_ifc_calc_op calc1; + struct mlx5_ifc_calc_op calc2; + struct mlx5_ifc_calc_op calc3; + + u8 reserved_at_e0[0x720]; +}; + enum { MLX5_WQ_TYPE_LINKED_LIST = 0x0, MLX5_WQ_TYPE_CYCLIC = 0x1, @@ -781,7 +808,8 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 cd[0x1]; u8 reserved_at_22c[0x1]; u8 apm[0x1]; - u8 reserved_at_22e[0x7]; + u8 vector_calc[0x1]; + u8 reserved_at_22f[0x6]; u8 qkv[0x1]; u8 pkv[0x1]; u8 reserved_at_237[0x4]; @@ -1918,6 +1946,7 @@ union mlx5_ifc_hca_cap_union_bits { struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; struct mlx5_ifc_e_switch_cap_bits e_switch_cap; + struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; u8 reserved_at_0[0x8000]; };