From patchwork Sat Sep 30 09:28:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wei Hu (Xavier)" X-Patchwork-Id: 9979311 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 81AEF6034B for ; Sat, 30 Sep 2017 09:01:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6D30E295A4 for ; Sat, 30 Sep 2017 09:01:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6199628AA0; Sat, 30 Sep 2017 09:01:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CBA5C28AA0 for ; Sat, 30 Sep 2017 09:01:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752664AbdI3JBS (ORCPT ); Sat, 30 Sep 2017 05:01:18 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:7489 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752648AbdI3JBB (ORCPT ); Sat, 30 Sep 2017 05:01:01 -0400 Received: from 172.30.72.60 (EHLO DGGEMS401-HUB.china.huawei.com) ([172.30.72.60]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DIF88303; Sat, 30 Sep 2017 17:00:59 +0800 (CST) Received: from linux-ioko.site (10.71.200.31) by DGGEMS401-HUB.china.huawei.com (10.3.19.201) with Microsoft SMTP Server id 14.3.301.0; Sat, 30 Sep 2017 17:00:51 +0800 From: "Wei Hu (Xavier)" To: CC: , , , , , , , , , , , , Subject: [PATCH for-next 2/4] RDMA/hns: Add IOMMU enable support in hip08 Date: Sat, 30 Sep 2017 17:28:59 +0800 Message-ID: <1506763741-81429-3-git-send-email-xavier.huwei@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506763741-81429-1-git-send-email-xavier.huwei@huawei.com> References: <1506763741-81429-1-git-send-email-xavier.huwei@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.71.200.31] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A0B0207.59CF5D4B.00F6, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: ad88e9631cbef0c5d14974b7f0272535 Sender: linux-rdma-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-rdma@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP If the IOMMU is enabled, the length of sg obtained from __iommu_map_sg_attrs is not 4kB. When the IOVA is set with the sg dma address, the IOVA will not be page continuous. and the VA returned from dma_alloc_coherent is a vmalloc address. However, the VA obtained by the page_address is a discontinuous VA. Under these circumstances, the IOVA should be calculated based on the sg length, and record the VA returned from dma_alloc_coherent in the struct of hem. Signed-off-by: Wei Hu (Xavier) Signed-off-by: Shaobo Xu Signed-off-by: Lijun Ou --- drivers/infiniband/hw/hns/hns_roce_alloc.c | 5 ++++- drivers/infiniband/hw/hns/hns_roce_hem.c | 30 +++++++++++++++++++++++++++--- drivers/infiniband/hw/hns/hns_roce_hem.h | 6 ++++++ drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 22 +++++++++++++++------- 4 files changed, 52 insertions(+), 11 deletions(-) diff --git a/drivers/infiniband/hw/hns/hns_roce_alloc.c b/drivers/infiniband/hw/hns/hns_roce_alloc.c index 3e4c525..a69cd4b 100644 --- a/drivers/infiniband/hw/hns/hns_roce_alloc.c +++ b/drivers/infiniband/hw/hns/hns_roce_alloc.c @@ -243,7 +243,10 @@ int hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, u32 max_direct, goto err_free; for (i = 0; i < buf->nbufs; ++i) - pages[i] = virt_to_page(buf->page_list[i].buf); + pages[i] = + is_vmalloc_addr(buf->page_list[i].buf) ? + vmalloc_to_page(buf->page_list[i].buf) : + virt_to_page(buf->page_list[i].buf); buf->direct.buf = vmap(pages, buf->nbufs, VM_MAP, PAGE_KERNEL); diff --git a/drivers/infiniband/hw/hns/hns_roce_hem.c b/drivers/infiniband/hw/hns/hns_roce_hem.c index 8388ae2..4a3d1d4 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hem.c +++ b/drivers/infiniband/hw/hns/hns_roce_hem.c @@ -200,6 +200,7 @@ static struct hns_roce_hem *hns_roce_alloc_hem(struct hns_roce_dev *hr_dev, gfp_t gfp_mask) { struct hns_roce_hem_chunk *chunk = NULL; + struct hns_roce_vmalloc *vmalloc; struct hns_roce_hem *hem; struct scatterlist *mem; int order; @@ -227,6 +228,7 @@ static struct hns_roce_hem *hns_roce_alloc_hem(struct hns_roce_dev *hr_dev, sg_init_table(chunk->mem, HNS_ROCE_HEM_CHUNK_LEN); chunk->npages = 0; chunk->nsg = 0; + memset(chunk->vmalloc, 0, sizeof(chunk->vmalloc)); list_add_tail(&chunk->list, &hem->chunk_list); } @@ -243,7 +245,15 @@ static struct hns_roce_hem *hns_roce_alloc_hem(struct hns_roce_dev *hr_dev, if (!buf) goto fail; - sg_set_buf(mem, buf, PAGE_SIZE << order); + if (is_vmalloc_addr(buf)) { + vmalloc = &chunk->vmalloc[chunk->npages]; + vmalloc->is_vmalloc_addr = true; + vmalloc->vmalloc_addr = buf; + sg_set_page(mem, vmalloc_to_page(buf), + PAGE_SIZE << order, offset_in_page(buf)); + } else { + sg_set_buf(mem, buf, PAGE_SIZE << order); + } WARN_ON(mem->offset); sg_dma_len(mem) = PAGE_SIZE << order; @@ -262,17 +272,25 @@ static struct hns_roce_hem *hns_roce_alloc_hem(struct hns_roce_dev *hr_dev, void hns_roce_free_hem(struct hns_roce_dev *hr_dev, struct hns_roce_hem *hem) { struct hns_roce_hem_chunk *chunk, *tmp; + void *cpu_addr; int i; if (!hem) return; list_for_each_entry_safe(chunk, tmp, &hem->chunk_list, list) { - for (i = 0; i < chunk->npages; ++i) + for (i = 0; i < chunk->npages; ++i) { + if (chunk->vmalloc[i].is_vmalloc_addr) + cpu_addr = chunk->vmalloc[i].vmalloc_addr; + else + cpu_addr = + lowmem_page_address(sg_page(&chunk->mem[i])); + dma_free_coherent(hr_dev->dev, chunk->mem[i].length, - lowmem_page_address(sg_page(&chunk->mem[i])), + cpu_addr, sg_dma_address(&chunk->mem[i])); + } kfree(chunk); } @@ -774,6 +792,12 @@ void *hns_roce_table_find(struct hns_roce_dev *hr_dev, if (chunk->mem[i].length > (u32)offset) { page = sg_page(&chunk->mem[i]); + if (chunk->vmalloc[i].is_vmalloc_addr) { + mutex_unlock(&table->mutex); + return page ? + chunk->vmalloc[i].vmalloc_addr + + offset : NULL; + } goto out; } offset -= chunk->mem[i].length; diff --git a/drivers/infiniband/hw/hns/hns_roce_hem.h b/drivers/infiniband/hw/hns/hns_roce_hem.h index af28bbf..62d712a 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hem.h +++ b/drivers/infiniband/hw/hns/hns_roce_hem.h @@ -72,11 +72,17 @@ enum { HNS_ROCE_HEM_PAGE_SIZE = 1 << HNS_ROCE_HEM_PAGE_SHIFT, }; +struct hns_roce_vmalloc { + bool is_vmalloc_addr; + void *vmalloc_addr; +}; + struct hns_roce_hem_chunk { struct list_head list; int npages; int nsg; struct scatterlist mem[HNS_ROCE_HEM_CHUNK_LEN]; + struct hns_roce_vmalloc vmalloc[HNS_ROCE_HEM_CHUNK_LEN]; }; struct hns_roce_hem { diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c index b99d70a..9e19bf1 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c @@ -1093,9 +1093,11 @@ static int hns_roce_v2_write_mtpt(void *mb_buf, struct hns_roce_mr *mr, { struct hns_roce_v2_mpt_entry *mpt_entry; struct scatterlist *sg; + u64 page_addr = 0; u64 *pages; + int i = 0, j = 0; + int len = 0; int entry; - int i; mpt_entry = mb_buf; memset(mpt_entry, 0, sizeof(*mpt_entry)); @@ -1153,14 +1155,20 @@ static int hns_roce_v2_write_mtpt(void *mb_buf, struct hns_roce_mr *mr, i = 0; for_each_sg(mr->umem->sg_head.sgl, sg, mr->umem->nmap, entry) { - pages[i] = ((u64)sg_dma_address(sg)) >> 6; - - /* Record the first 2 entry directly to MTPT table */ - if (i >= HNS_ROCE_V2_MAX_INNER_MTPT_NUM - 1) - break; - i++; + len = sg_dma_len(sg) >> PAGE_SHIFT; + for (j = 0; j < len; ++j) { + page_addr = sg_dma_address(sg) + + (j << mr->umem->page_shift); + pages[i] = page_addr >> 6; + + /* Record the first 2 entry directly to MTPT table */ + if (i >= HNS_ROCE_V2_MAX_INNER_MTPT_NUM - 1) + goto found; + i++; + } } +found: mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0])); roce_set_field(mpt_entry->byte_56_pa0_h, V2_MPT_BYTE_56_PA0_H_M, V2_MPT_BYTE_56_PA0_H_S,