@@ -114,6 +114,10 @@ struct mlx5_alloc_pd_resp {
__u32 pdn;
};
+enum mlx5_create_cq_flags {
+ MLX5_CREATE_CQ_FLAGS_CQE_128B_PAD = 1 << 0,
+};
+
struct mlx5_create_cq {
struct ibv_create_cq ibv_cmd;
__u64 buf_addr;
@@ -121,7 +125,7 @@ struct mlx5_create_cq {
__u32 cqe_size;
__u8 cqe_comp_en;
__u8 cqe_comp_res_format;
- __u16 reserved;
+ __u16 flags; /* Use enum mlx5_create_cq_flags */
};
struct mlx5_create_cq_resp {
@@ -98,12 +98,19 @@ enum mlx5dv_context_flags {
enum mlx5dv_cq_init_attr_mask {
MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE = 1 << 0,
- MLX5DV_CQ_INIT_ATTR_MASK_RESERVED = 1 << 1,
+ MLX5DV_CQ_INIT_ATTR_MASK_FLAGS = 1 << 1,
+ MLX5DV_CQ_INIT_ATTR_MASK_RESERVED = 1 << 2,
+};
+
+enum mlx5dv_cq_init_attr_flags {
+ MLX5DV_CQ_INIT_ATTR_FLAGS_CQE_PAD = 1 << 0,
+ MLX5DV_CQ_INIT_ATTR_FLAGS_RESERVED = 1 << 1,
};
struct mlx5dv_cq_init_attr {
uint64_t comp_mask; /* Use enum mlx5dv_cq_init_attr_mask */
uint8_t cqe_comp_res_format; /* Use enum mlx5dv_cqe_comp_res_format */
+ uint32_t flags; /* Use enum mlx5dv_cq_init_attr_flags */
};
struct ibv_cq_ex *mlx5dv_create_cq(struct ibv_context *context,
@@ -453,6 +453,29 @@ static struct ibv_cq_ex *create_cq(struct ibv_context *context,
goto err_db;
}
}
+
+ if (mlx5cq_attr->comp_mask & MLX5DV_CQ_INIT_ATTR_MASK_FLAGS) {
+ if (mlx5cq_attr->flags & ~(MLX5DV_CQ_INIT_ATTR_FLAGS_RESERVED - 1)) {
+ mlx5_dbg(fp, MLX5_DBG_CQ,
+ "Unsupported vendor flags for create_cq\n");
+ errno = EINVAL;
+ goto err_db;
+ }
+
+ if (mlx5cq_attr->flags & MLX5DV_CQ_INIT_ATTR_FLAGS_CQE_PAD) {
+ if (!(mctx->vendor_cap_flags &
+ MLX5_VENDOR_CAP_FLAGS_CQE_128B_PAD) ||
+ (cqe_sz != 128)) {
+ mlx5_dbg(fp, MLX5_DBG_CQ,
+ "%dB CQE paddind is not supported\n",
+ cqe_sz);
+ errno = EINVAL;
+ goto err_db;
+ }
+
+ cmd.flags |= MLX5_CREATE_CQ_FLAGS_CQE_128B_PAD;
+ }
+ }
}
ret = ibv_cmd_create_cq(context, ncqe - 1, cq_attr->channel,