From patchwork Wed Nov 15 14:23:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yishai Hadas X-Patchwork-Id: 10059605 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 2DA72604D4 for ; Wed, 15 Nov 2017 14:24:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 22E7C2A069 for ; Wed, 15 Nov 2017 14:24:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 179992A076; Wed, 15 Nov 2017 14:24:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 81D5E2A06D for ; Wed, 15 Nov 2017 14:24:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755920AbdKOOYO (ORCPT ); Wed, 15 Nov 2017 09:24:14 -0500 Received: from mail-il-dmz.mellanox.com ([193.47.165.129]:58760 "EHLO mellanox.co.il" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754062AbdKOOYN (ORCPT ); Wed, 15 Nov 2017 09:24:13 -0500 Received: from Internal Mail-Server by MTLPINE1 (envelope-from yishaih@mellanox.com) with ESMTPS (AES256-SHA encrypted); 15 Nov 2017 16:24:08 +0200 Received: from vnc17.mtl.labs.mlnx (vnc17.mtl.labs.mlnx [10.7.2.17]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id vAFEO8rL031829; Wed, 15 Nov 2017 16:24:08 +0200 Received: from vnc17.mtl.labs.mlnx (vnc17.mtl.labs.mlnx [127.0.0.1]) by vnc17.mtl.labs.mlnx (8.13.8/8.13.8) with ESMTP id vAFEO8lb016116; Wed, 15 Nov 2017 16:24:08 +0200 Received: (from yishaih@localhost) by vnc17.mtl.labs.mlnx (8.13.8/8.13.8/Submit) id vAFEO8TS016115; Wed, 15 Nov 2017 16:24:08 +0200 From: Yishai Hadas To: linux-rdma@vger.kernel.org Cc: yishaih@mellanox.com, guyle@mellanox.com, majd@mellanox.com Subject: [PATCH rdma-core 3/3] mlx5: Support padded CQE by mlx5dv_create_cq Date: Wed, 15 Nov 2017 16:23:42 +0200 Message-Id: <1510755822-15945-4-git-send-email-yishaih@mellanox.com> X-Mailer: git-send-email 1.8.2.3 In-Reply-To: <1510755822-15945-1-git-send-email-yishaih@mellanox.com> References: <1510755822-15945-1-git-send-email-yishaih@mellanox.com> Sender: linux-rdma-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-rdma@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Guy Levi This patch enables creating a padded 128B CQE using the direct verb mlx5dv_create_cq. Signed-off-by: Guy Levi Reviewed-by: Yishai Hadas --- providers/mlx5/mlx5-abi.h | 6 +++++- providers/mlx5/mlx5dv.h | 9 ++++++++- providers/mlx5/verbs.c | 23 +++++++++++++++++++++++ 3 files changed, 36 insertions(+), 2 deletions(-) diff --git a/providers/mlx5/mlx5-abi.h b/providers/mlx5/mlx5-abi.h index 574688a..e1f5114 100644 --- a/providers/mlx5/mlx5-abi.h +++ b/providers/mlx5/mlx5-abi.h @@ -114,6 +114,10 @@ struct mlx5_alloc_pd_resp { __u32 pdn; }; +enum mlx5_create_cq_flags { + MLX5_CREATE_CQ_FLAGS_CQE_128B_PAD = 1 << 0, +}; + struct mlx5_create_cq { struct ibv_create_cq ibv_cmd; __u64 buf_addr; @@ -121,7 +125,7 @@ struct mlx5_create_cq { __u32 cqe_size; __u8 cqe_comp_en; __u8 cqe_comp_res_format; - __u16 reserved; + __u16 flags; /* Use enum mlx5_create_cq_flags */ }; struct mlx5_create_cq_resp { diff --git a/providers/mlx5/mlx5dv.h b/providers/mlx5/mlx5dv.h index 0073b9c..935ff54 100644 --- a/providers/mlx5/mlx5dv.h +++ b/providers/mlx5/mlx5dv.h @@ -98,12 +98,19 @@ enum mlx5dv_context_flags { enum mlx5dv_cq_init_attr_mask { MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE = 1 << 0, - MLX5DV_CQ_INIT_ATTR_MASK_RESERVED = 1 << 1, + MLX5DV_CQ_INIT_ATTR_MASK_FLAGS = 1 << 1, + MLX5DV_CQ_INIT_ATTR_MASK_RESERVED = 1 << 2, +}; + +enum mlx5dv_cq_init_attr_flags { + MLX5DV_CQ_INIT_ATTR_FLAGS_CQE_PAD = 1 << 0, + MLX5DV_CQ_INIT_ATTR_FLAGS_RESERVED = 1 << 1, }; struct mlx5dv_cq_init_attr { uint64_t comp_mask; /* Use enum mlx5dv_cq_init_attr_mask */ uint8_t cqe_comp_res_format; /* Use enum mlx5dv_cqe_comp_res_format */ + uint32_t flags; /* Use enum mlx5dv_cq_init_attr_flags */ }; struct ibv_cq_ex *mlx5dv_create_cq(struct ibv_context *context, diff --git a/providers/mlx5/verbs.c b/providers/mlx5/verbs.c index 7350697..19fc947 100644 --- a/providers/mlx5/verbs.c +++ b/providers/mlx5/verbs.c @@ -453,6 +453,29 @@ static struct ibv_cq_ex *create_cq(struct ibv_context *context, goto err_db; } } + + if (mlx5cq_attr->comp_mask & MLX5DV_CQ_INIT_ATTR_MASK_FLAGS) { + if (mlx5cq_attr->flags & ~(MLX5DV_CQ_INIT_ATTR_FLAGS_RESERVED - 1)) { + mlx5_dbg(fp, MLX5_DBG_CQ, + "Unsupported vendor flags for create_cq\n"); + errno = EINVAL; + goto err_db; + } + + if (mlx5cq_attr->flags & MLX5DV_CQ_INIT_ATTR_FLAGS_CQE_PAD) { + if (!(mctx->vendor_cap_flags & + MLX5_VENDOR_CAP_FLAGS_CQE_128B_PAD) || + (cqe_sz != 128)) { + mlx5_dbg(fp, MLX5_DBG_CQ, + "%dB CQE paddind is not supported\n", + cqe_sz); + errno = EINVAL; + goto err_db; + } + + cmd.flags |= MLX5_CREATE_CQ_FLAGS_CQE_128B_PAD; + } + } } ret = ibv_cmd_create_cq(context, ncqe - 1, cq_attr->channel,