From patchwork Wed Mar 21 18:09:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yishai Hadas X-Patchwork-Id: 10299985 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0A521600F6 for ; Wed, 21 Mar 2018 18:10:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EA5AB298D3 for ; Wed, 21 Mar 2018 18:10:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E909F298E7; Wed, 21 Mar 2018 18:10:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 47C78298E2 for ; Wed, 21 Mar 2018 18:10:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752519AbeCUSKb (ORCPT ); Wed, 21 Mar 2018 14:10:31 -0400 Received: from mail-il-dmz.mellanox.com ([193.47.165.129]:57471 "EHLO mellanox.co.il" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752522AbeCUSK0 (ORCPT ); Wed, 21 Mar 2018 14:10:26 -0400 Received: from Internal Mail-Server by MTLPINE1 (envelope-from yishaih@mellanox.com) with ESMTPS (AES256-SHA encrypted); 21 Mar 2018 20:11:08 +0200 Received: from vnc17.mtl.labs.mlnx (vnc17.mtl.labs.mlnx [10.7.2.17]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id w2LIAKKi014359; Wed, 21 Mar 2018 20:10:20 +0200 Received: from vnc17.mtl.labs.mlnx (vnc17.mtl.labs.mlnx [127.0.0.1]) by vnc17.mtl.labs.mlnx (8.13.8/8.13.8) with ESMTP id w2LIAKI0007797; Wed, 21 Mar 2018 20:10:20 +0200 Received: (from yishaih@localhost) by vnc17.mtl.labs.mlnx (8.13.8/8.13.8/Submit) id w2LIAK5p007796; Wed, 21 Mar 2018 20:10:20 +0200 From: Yishai Hadas To: linux-rdma@vger.kernel.org Cc: yishaih@mellanox.com, matanb@mellanox.com, jgg@mellanox.com, majd@mellanox.com Subject: [PATCH rdma-core 10/11] mlx5: Query the FLOW_ACTION capabilities through DV Date: Wed, 21 Mar 2018 20:09:59 +0200 Message-Id: <1521655800-7287-11-git-send-email-yishaih@mellanox.com> X-Mailer: git-send-email 1.8.2.3 In-Reply-To: <1521655800-7287-1-git-send-email-yishaih@mellanox.com> References: <1521655800-7287-1-git-send-email-yishaih@mellanox.com> Sender: linux-rdma-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-rdma@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Matan Barak Some applications which use DV verbs would like to query the FLOW_ACTION capabilities. This could be done through mlx5dv_query_device DV verb. The semantics for these capabilities are as follows: MLX5DV_FLOW_ACTION_FLAGS_ESP_AES_GCM Support ESP (with AES_GCM keymat) MLX5DV_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA ESP (with AES_GCM keymat) actions require parsing of metadata which is returned as part of the payload. MLX5DV_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING Zero means that we can't match against SPI, but we can RSS using this field. MLX5DV_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD ESP (with AES_GCM keymat) supports full offload mode MLX5DV_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN In ESP (with AES_GCM keymat) ESN comes implicitly from the IV. Signed-off-by: Matan Barak Signed-off-by: Yishai Hadas --- providers/mlx5/man/mlx5dv_query_device.3 | 12 ++++++++++++ providers/mlx5/mlx5-abi.h | 2 +- providers/mlx5/mlx5.c | 7 +++++++ providers/mlx5/mlx5.h | 1 + providers/mlx5/mlx5dv.h | 10 ++++++++++ 5 files changed, 31 insertions(+), 1 deletion(-) diff --git a/providers/mlx5/man/mlx5dv_query_device.3 b/providers/mlx5/man/mlx5dv_query_device.3 index 522b054..feb2cb1 100644 --- a/providers/mlx5/man/mlx5dv_query_device.3 +++ b/providers/mlx5/man/mlx5dv_query_device.3 @@ -99,6 +99,18 @@ MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE = 1 << 2, .in -8 }; +.PP +.nf +enum mlx5dv_flow_action_cap_flags { +.in +8 +MLX5DV_FLOW_ACTION_FLAGS_ESP_AES_GCM = 1 << 0, /* Flow action ESP (with AES_GCM keymat) is supported */ +MLX5DV_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA = 1 << 1, /* Flow action ESP always return metadata in the payload */ +MLX5DV_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING = 1 << 2, /* ESP (with AESGCM keymat) Supports matching by SPI (rather than hashing against SPI) */ +MLX5DV_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD = 1 << 3, /* Flow action ESP supports full offload (with AES_GCM keymat) */ +MLX5DV_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN = 1 << 4, /* Flow action ESP (with AES_GCM keymat), ESN comes implicitly from IV. */ +.in -8 +}; + .fi .SH "RETURN VALUE" 0 on success or the value of errno on failure (which indicates the failure reason). diff --git a/providers/mlx5/mlx5-abi.h b/providers/mlx5/mlx5-abi.h index dded202..1b8f35f 100644 --- a/providers/mlx5/mlx5-abi.h +++ b/providers/mlx5/mlx5-abi.h @@ -116,7 +116,7 @@ struct mlx5_alloc_ucontext_resp { __u32 max_recv_wr; __u32 max_srq_recv_wr; __u16 num_ports; - __u16 reserved1; + __u16 flow_action_flags; __u32 comp_mask; __u32 response_length; __u8 cqe_version; diff --git a/providers/mlx5/mlx5.c b/providers/mlx5/mlx5.c index 8878194..eb8d977 100644 --- a/providers/mlx5/mlx5.c +++ b/providers/mlx5/mlx5.c @@ -712,6 +712,11 @@ int mlx5dv_query_device(struct ibv_context *ctx_in, } } + if (attrs_out->comp_mask & MLX5DV_CONTEXT_MASK_FLOW_ACTION_FLAGS) { + attrs_out->flow_action_flags = mctx->flow_action_flags; + comp_mask_out |= MLX5DV_CONTEXT_MASK_FLOW_ACTION_FLAGS; + } + attrs_out->comp_mask = comp_mask_out; return 0; @@ -1122,6 +1127,8 @@ static struct verbs_context *mlx5_alloc_context(struct ibv_device *ibdev, mlx5_map_clock_info(mdev, &v_ctx->context); } + context->flow_action_flags = resp.flow_action_flags; + mlx5_read_env(ibdev, context); mlx5_spinlock_init(&context->hugetlb_lock); diff --git a/providers/mlx5/mlx5.h b/providers/mlx5/mlx5.h index 18895db..4c98dac 100644 --- a/providers/mlx5/mlx5.h +++ b/providers/mlx5/mlx5.h @@ -303,6 +303,7 @@ struct mlx5_context { uint32_t num_dyn_bfregs; uint32_t *count_dyn_bfregs; uint32_t start_dyn_bfregs_index; + uint16_t flow_action_flags; }; struct mlx5_bitmap { diff --git a/providers/mlx5/mlx5dv.h b/providers/mlx5/mlx5dv.h index 37aee18..a990c1e 100644 --- a/providers/mlx5/mlx5dv.h +++ b/providers/mlx5/mlx5dv.h @@ -70,6 +70,7 @@ enum mlx5dv_context_comp_mask { MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS = 1 << 3, MLX5DV_CONTEXT_MASK_DYN_BFREGS = 1 << 4, MLX5DV_CONTEXT_MASK_CLOCK_INFO_UPDATE = 1 << 5, + MLX5DV_CONTEXT_MASK_FLOW_ACTION_FLAGS = 1 << 6, }; struct mlx5dv_cqe_comp_caps { @@ -96,6 +97,14 @@ enum mlx5dv_tunnel_offloads { MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE = 1 << 2, }; +enum mlx5dv_flow_action_cap_flags { + MLX5DV_FLOW_ACTION_FLAGS_ESP_AES_GCM = 1 << 0, + MLX5DV_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA = 1 << 1, + MLX5DV_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING = 1 << 2, + MLX5DV_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD = 1 << 3, + MLX5DV_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN = 1 << 4, +}; + /* * Direct verbs device-specific attributes */ @@ -109,6 +118,7 @@ struct mlx5dv_context { uint32_t tunnel_offloads_caps; uint32_t max_dynamic_bfregs; uint64_t max_clock_info_update_nsec; + uint32_t flow_action_flags; /* use enum mlx5dv_flow_action_cap_flags */ }; enum mlx5dv_context_flags {