diff mbox series

[rdma-core,1/3] mlx5: Infrastructure for building mailbox for devx

Message ID 1548590494-16684-2-git-send-email-yishaih@mellanox.com (mailing list archive)
State Not Applicable
Headers show
Series Expose PCI atomic capabilities | expand

Commit Message

Yishai Hadas Jan. 27, 2019, 12:01 p.m. UTC 
From: Michael Guralnik <michaelgur@mellanox.com>

When using the devx interface a user needs to build and parse mailboxes
to and from firmware based on predefined structures.  In the kernel this
is done using a set of getters and setters. This commit introduces this
infrastructure to the user-space.

Signed-off-by: Michael Guralnik <michaelgur@mellanox.com>
Signed-off-by: Yishai Hadas <yishaih@mellanox.com>
---
 providers/mlx5/mlx5dv.h | 59 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 59 insertions(+)
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Patch

diff --git a/providers/mlx5/mlx5dv.h b/providers/mlx5/mlx5dv.h
index 416cf92..8c76713 100644
--- a/providers/mlx5/mlx5dv.h
+++ b/providers/mlx5/mlx5dv.h
@@ -1169,6 +1169,65 @@  int mlx5dv_devx_ind_tbl_modify(struct ibv_rwq_ind_table *ind_tbl,
 			       const void *in, size_t inlen,
 			       void *out, size_t outlen);
 
+#define __devx_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)NULL)
+#define __devx_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
+#define __devx_bit_sz(typ, fld) sizeof(__devx_nullp(typ)->fld)
+#define __devx_bit_off(typ, fld) offsetof(struct mlx5_ifc_##typ##_bits, fld)
+#define __devx_dw_off(bit_off) ((bit_off) / 32)
+#define __devx_64_off(bit_off) ((bit_off) / 64)
+#define __devx_dw_bit_off(bit_sz, bit_off) (32 - (bit_sz) - ((bit_off) & 0x1f))
+#define __devx_mask(bit_sz) ((uint32_t)((1ull << (bit_sz)) - 1))
+#define __devx_dw_mask(bit_sz, bit_off)                                        \
+	(__devx_mask(bit_sz) << __devx_dw_bit_off(bit_sz, bit_off))
+
+#define DEVX_FLD_SZ_BYTES(typ, fld) (__devx_bit_sz(typ, fld) / 8)
+#define DEVX_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
+#define DEVX_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
+#define DEVX_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64)
+#define DEVX_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
+#define DEVX_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
+#define DEVX_BYTE_OFF(typ, fld) (__devx_bit_off(typ, fld) / 8)
+#define DEVX_ADDR_OF(typ, p, fld)                                              \
+	((unsigned char *)(p) + DEVX_BYTE_OFF(typ, fld))
+
+static inline void _devx_set(void *p, uint32_t value, size_t bit_off,
+			     size_t bit_sz)
+{
+	__be32 *fld = (__be32 *)(p) + __devx_dw_off(bit_off);
+	uint32_t dw_mask = __devx_dw_mask(bit_sz, bit_off);
+	uint32_t mask = __devx_mask(bit_sz);
+
+	*fld = htobe32((be32toh(*fld) & (~dw_mask)) |
+		       ((value & mask) << __devx_dw_bit_off(bit_sz, bit_off)));
+}
+
+#define DEVX_SET(typ, p, fld, v)                                               \
+	_devx_set(p, v, __devx_bit_off(typ, fld), __devx_bit_sz(typ, fld))
+
+static inline uint32_t _devx_get(const void *p, size_t bit_off, size_t bit_sz)
+{
+	return ((be32toh(*((__be32 *)(p) + __devx_dw_off(bit_off))) >>
+		 __devx_dw_bit_off(bit_sz, bit_off)) &
+		__devx_mask(bit_sz));
+}
+
+#define DEVX_GET(typ, p, fld)                                                  \
+	_devx_get(p, __devx_bit_off(typ, fld), __devx_bit_sz(typ, fld))
+
+static inline void _devx_set64(void *p, uint64_t v, size_t bit_off)
+{
+	*((__be64 *)(p) + __devx_64_off(bit_off)) = htobe64(v);
+}
+
+#define DEVX_SET64(typ, p, fld, v) _devx_set64(p, v, __devx_bit_off(typ, fld))
+
+static inline uint64_t _devx_get64(void *p, size_t bit_off)
+{
+	return be64toh(*((__be64 *)(p) + __devx_64_off(bit_off)));
+}
+
+#define DEVX_GET64(typ, p, fld) _devx_get64(p, __devx_bit_off(typ, fld))
+
 #ifdef __cplusplus
 }
 #endif