From patchwork Wed Sep 23 07:36:58 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eli Cohen X-Patchwork-Id: 49490 Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n8N7b8oH025809 for ; Wed, 23 Sep 2009 07:37:08 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754411AbZIWHgp (ORCPT ); Wed, 23 Sep 2009 03:36:45 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1754489AbZIWHgo (ORCPT ); Wed, 23 Sep 2009 03:36:44 -0400 Received: from mail.mellanox.co.il ([194.90.237.43]:49715 "EHLO mellanox.co.il" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754411AbZIWHgm (ORCPT ); Wed, 23 Sep 2009 03:36:42 -0400 Received: from Internal Mail-Server by MTLPINE1 (envelope-from eli@mellanox.co.il) with SMTP; 23 Sep 2009 10:38:23 +0300 Received: from localhost ([10.4.1.30]) by mtlexch01.mtl.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 23 Sep 2009 10:36:42 +0300 Date: Wed, 23 Sep 2009 10:36:58 +0300 From: Eli Cohen To: Roland Dreier Cc: general-list , linux-rdma@vger.kernel.org Subject: [PATCH v2] mlx4: configure cache line size Message-ID: <20090923073658.GA23252@mtls03> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.18 (2008-05-17) X-OriginalArrivalTime: 23 Sep 2009 07:36:42.0830 (UTC) FILETIME=[987B06E0:01CA3C20] X-TM-AS-Product-Ver: SMEX-8.0.0.1181-5.600.1016-16904.004 X-TM-AS-Result: No--5.043100-8.000000-31 X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No Sender: linux-rdma-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-rdma@vger.kernel.org ConnectX can work more efficiently if the CPU cache line size is configured to it at INIT_HCA. This patch configures the CPU cache line size. Signed-off-by: Eli Cohen --- As per Roland's comments, the following changes were made: 1. Remove #ifdef cache_line_size and include linux/cache.h 2. Assume cache line size is a power of 2 and use ilog2 instead of order_base_2 drivers/net/mlx4/fw.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/drivers/net/mlx4/fw.c b/drivers/net/mlx4/fw.c index cee199c..3c16602 100644 --- a/drivers/net/mlx4/fw.c +++ b/drivers/net/mlx4/fw.c @@ -33,6 +33,7 @@ */ #include +#include #include "fw.h" #include "icm.h" @@ -698,6 +699,7 @@ int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param) #define INIT_HCA_IN_SIZE 0x200 #define INIT_HCA_VERSION_OFFSET 0x000 #define INIT_HCA_VERSION 2 +#define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e #define INIT_HCA_FLAGS_OFFSET 0x014 #define INIT_HCA_QPC_OFFSET 0x020 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10) @@ -735,6 +737,9 @@ int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param) *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION; + *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) = + (ilog2(cache_line_size()) - 4) << 5; + #if defined(__LITTLE_ENDIAN) *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1); #elif defined(__BIG_ENDIAN)