From patchwork Wed May 26 15:36:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Devesh Sharma X-Patchwork-Id: 12282157 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9BACC47088 for ; Wed, 26 May 2021 15:36:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A9E3961002 for ; Wed, 26 May 2021 15:36:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232913AbhEZPiR (ORCPT ); Wed, 26 May 2021 11:38:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48992 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233675AbhEZPiQ (ORCPT ); Wed, 26 May 2021 11:38:16 -0400 Received: from mail-pj1-x1036.google.com (mail-pj1-x1036.google.com [IPv6:2607:f8b0:4864:20::1036]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 32BB8C061756 for ; Wed, 26 May 2021 08:36:45 -0700 (PDT) Received: by mail-pj1-x1036.google.com with SMTP id k5so1008708pjj.1 for ; Wed, 26 May 2021 08:36:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version; bh=IkeI+ydRt/4XYMLwmEyfljlSDRLCvkCSMtIwLATLWDc=; b=FNOb6pVdCAfqnRhv0iGjlPNeNnyEOSRtfOgTMLSczkoO/y7+3t868CqRJfs8qtkVk5 IIy3i9uQ+O9LN1kSWejOq9RdeP5KMpZJRULxZXGjQ+yQQigLRvedkpyN0grHH7ax02x/ 59mFzAhSBEZZ46o8iCIi5vo2/F5Dl/ChhUHL0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version; bh=IkeI+ydRt/4XYMLwmEyfljlSDRLCvkCSMtIwLATLWDc=; b=h0y88PIWQJC7UVywF/0CsU/J5tw+wpAre94xmNeIyu82+sGnZPHx6k3dE5iduf91sn DaQnt2xf58iSAiFG0BF5nycdEOzT1z0iAPKH3vHz1fFe3g2wWHZp6zlzNSqPVH0M5F1h 4FmNiqZXvlYnNAFKezLstvyP2NBN0tLIc+G5BgmaRKJrm/1FLxo3CLCY9v6i/MkO8aK4 egxzUHZLukiOhX0qrsQrz+qGk+HIJwmXIi+Hxx+QqveoDxXC8syTXxlCpu9DDCbXWmPC uK2kwVVZ0QZ+AA1Btt52jU8R5/WleklEBd1LfgqVctHAESYeUXPPhN/+4vkw8SnEXB5W zzUg== X-Gm-Message-State: AOAM531kXvU6cbxzIQAmVx26YnkADwSXt97QmZT+j4tEiEPIPUoMKstj yjVZM2PbR+F9FdOdyb2fSW0Zlx7mNJ6iR/+KRfD68P44GRLd3SF6AoRwIxUCvjG2FkYkhCxSYlv EOmLMek1s9kyCBk7ZmGZxQ3x54NkUh1EWwcZ+/AsVSyD+YR2NpQK6vO3DapPX0Cpu+7JIoe6RYP UQUQNtybia X-Google-Smtp-Source: ABdhPJyBW5ah5Acwy0JIiqV5ULNYmg1MZ0XU1GxtNpcmtsQZEuJwUWclByVP0O0kCYvPlVHBGZdVVw== X-Received: by 2002:a17:90a:7bcc:: with SMTP id d12mr4644400pjl.230.1622043403846; Wed, 26 May 2021 08:36:43 -0700 (PDT) Received: from dev01.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id 125sm15887052pfg.52.2021.05.26.08.36.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 May 2021 08:36:43 -0700 (PDT) From: Devesh Sharma To: linux-rdma@vger.kernel.org Cc: Devesh Sharma Subject: [PATCH for-next V3 1/3] RDMA/bnxt_re: Enable global atomic ops if platform supports Date: Wed, 26 May 2021 21:06:27 +0530 Message-Id: <20210526153629.872796-2-devesh.sharma@broadcom.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210526153629.872796-1-devesh.sharma@broadcom.com> References: <20210526153629.872796-1-devesh.sharma@broadcom.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-rdma@vger.kernel.org Enabling Atomic operations for Gen P5 devices if the underlying platform supports global atomic ops. Fixes:7ff662b76167 ("Disable atomic capability on bnxt_re adapters") Signed-off-by: Devesh Sharma --- drivers/infiniband/hw/bnxt_re/ib_verbs.c | 4 ++++ drivers/infiniband/hw/bnxt_re/main.c | 4 ++++ drivers/infiniband/hw/bnxt_re/qplib_res.c | 15 +++++++++++++++ drivers/infiniband/hw/bnxt_re/qplib_res.h | 1 + drivers/infiniband/hw/bnxt_re/qplib_sp.c | 13 ++++++++++++- drivers/infiniband/hw/bnxt_re/qplib_sp.h | 2 -- 6 files changed, 36 insertions(+), 3 deletions(-) diff --git a/drivers/infiniband/hw/bnxt_re/ib_verbs.c b/drivers/infiniband/hw/bnxt_re/ib_verbs.c index 537471ffaa79..a113d8d9e9ed 100644 --- a/drivers/infiniband/hw/bnxt_re/ib_verbs.c +++ b/drivers/infiniband/hw/bnxt_re/ib_verbs.c @@ -163,6 +163,10 @@ int bnxt_re_query_device(struct ib_device *ibdev, ib_attr->max_qp_init_rd_atom = dev_attr->max_qp_init_rd_atom; ib_attr->atomic_cap = IB_ATOMIC_NONE; ib_attr->masked_atomic_cap = IB_ATOMIC_NONE; + if (dev_attr->is_atomic) { + ib_attr->atomic_cap = IB_ATOMIC_GLOB; + ib_attr->masked_atomic_cap = IB_ATOMIC_GLOB; + } ib_attr->max_ee_rd_atom = 0; ib_attr->max_res_rd_atom = 0; diff --git a/drivers/infiniband/hw/bnxt_re/main.c b/drivers/infiniband/hw/bnxt_re/main.c index b090dfa4f4cb..ee0cdf89eb1a 100644 --- a/drivers/infiniband/hw/bnxt_re/main.c +++ b/drivers/infiniband/hw/bnxt_re/main.c @@ -128,6 +128,10 @@ static int bnxt_re_setup_chip_ctx(struct bnxt_re_dev *rdev, u8 wqe_mode) rdev->rcfw.res = &rdev->qplib_res; bnxt_re_set_drv_mode(rdev, wqe_mode); + if (bnxt_qplib_determine_atomics(en_dev->pdev)) + ibdev_info(&rdev->ibdev, + "platform doesn't support global atomics."); + return 0; } diff --git a/drivers/infiniband/hw/bnxt_re/qplib_res.c b/drivers/infiniband/hw/bnxt_re/qplib_res.c index 3ca47004b752..4de9359c2028 100644 --- a/drivers/infiniband/hw/bnxt_re/qplib_res.c +++ b/drivers/infiniband/hw/bnxt_re/qplib_res.c @@ -959,3 +959,18 @@ int bnxt_qplib_alloc_res(struct bnxt_qplib_res *res, struct pci_dev *pdev, bnxt_qplib_free_res(res); return rc; } + +bool bnxt_qplib_determine_atomics(struct pci_dev *dev) +{ + u16 ctl2; + + if(pci_enable_atomic_ops_to_root(dev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) && + pci_enable_atomic_ops_to_root(dev, PCI_EXP_DEVCAP2_ATOMIC_COMP64)) + return true; /* Failure */ + pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &ctl2); + if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_REQ) + return 0; /* Success */ + pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, + PCI_EXP_DEVCTL2_ATOMIC_REQ); + return 0; /* Success */ +} diff --git a/drivers/infiniband/hw/bnxt_re/qplib_res.h b/drivers/infiniband/hw/bnxt_re/qplib_res.h index 7a1ab38b95da..fb7fde4fed56 100644 --- a/drivers/infiniband/hw/bnxt_re/qplib_res.h +++ b/drivers/infiniband/hw/bnxt_re/qplib_res.h @@ -373,6 +373,7 @@ void bnxt_qplib_free_ctx(struct bnxt_qplib_res *res, int bnxt_qplib_alloc_ctx(struct bnxt_qplib_res *res, struct bnxt_qplib_ctx *ctx, bool virt_fn, bool is_p5); +bool bnxt_qplib_determine_atomics(struct pci_dev *dev); static inline void bnxt_qplib_hwq_incr_prod(struct bnxt_qplib_hwq *hwq, u32 cnt) { diff --git a/drivers/infiniband/hw/bnxt_re/qplib_sp.c b/drivers/infiniband/hw/bnxt_re/qplib_sp.c index 049b3576302b..57407be16f27 100644 --- a/drivers/infiniband/hw/bnxt_re/qplib_sp.c +++ b/drivers/infiniband/hw/bnxt_re/qplib_sp.c @@ -54,6 +54,17 @@ const struct bnxt_qplib_gid bnxt_qplib_gid_zero = {{ 0, 0, 0, 0, 0, 0, 0, 0, /* Device */ +static u8 bnxt_qplib_is_atomic_cap(struct bnxt_qplib_rcfw *rcfw) +{ + u16 pcie_ctl2 = 0; + + if (!bnxt_qplib_is_chip_gen_p5(rcfw->res->cctx)) + return false; + + pcie_capability_read_word(rcfw->pdev, PCI_EXP_DEVCTL2, &pcie_ctl2); + return (pcie_ctl2 & PCI_EXP_DEVCTL2_ATOMIC_REQ); +} + static void bnxt_qplib_query_version(struct bnxt_qplib_rcfw *rcfw, char *fw_ver) { @@ -162,7 +173,7 @@ int bnxt_qplib_get_dev_attr(struct bnxt_qplib_rcfw *rcfw, attr->tqm_alloc_reqs[i * 4 + 3] = *(++tqm_alloc); } - attr->is_atomic = false; + attr->is_atomic = bnxt_qplib_is_atomic_cap(rcfw); bail: bnxt_qplib_rcfw_free_sbuf(rcfw, sbuf); return rc; diff --git a/drivers/infiniband/hw/bnxt_re/qplib_sp.h b/drivers/infiniband/hw/bnxt_re/qplib_sp.h index bc228340684f..260104783691 100644 --- a/drivers/infiniband/hw/bnxt_re/qplib_sp.h +++ b/drivers/infiniband/hw/bnxt_re/qplib_sp.h @@ -42,8 +42,6 @@ #define BNXT_QPLIB_RESERVED_QP_WRS 128 -#define PCI_EXP_DEVCTL2_ATOMIC_REQ 0x0040 - struct bnxt_qplib_dev_attr { #define FW_VER_ARR_LEN 4 u8 fw_ver[FW_VER_ARR_LEN];