From patchwork Thu Jun 3 13:15:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Devesh Sharma X-Patchwork-Id: 12297205 X-Patchwork-Delegate: jgg@ziepe.ca Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02DA1C47082 for ; Thu, 3 Jun 2021 13:16:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D809860C3F for ; Thu, 3 Jun 2021 13:16:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231421AbhFCNSg (ORCPT ); Thu, 3 Jun 2021 09:18:36 -0400 Received: from mail-pj1-f53.google.com ([209.85.216.53]:34613 "EHLO mail-pj1-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231396AbhFCNSg (ORCPT ); Thu, 3 Jun 2021 09:18:36 -0400 Received: by mail-pj1-f53.google.com with SMTP id g6-20020a17090adac6b029015d1a9a6f1aso3357624pjx.1 for ; Thu, 03 Jun 2021 06:16:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version; bh=xYwsUD1BXnCBKbiGHUr9TSQXmfXoXdq9LzssqA+jlA0=; b=XPCJPis2o9aDDUSDcBLeOT+Q2IvOmsMn/sWKAR5Evlt3LHXhC09bhTPOPDmpO7I63p XaW04hcbx0ia3Q2eEtg21RAX7wBEfoBE/ajko0DIHgH1GIrltbq67LCqnB8DeUUb2pJp X7zRxOD6ZKubilEhcW8GUv6U1jn8BDF9VGRkQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version; bh=xYwsUD1BXnCBKbiGHUr9TSQXmfXoXdq9LzssqA+jlA0=; b=acA+4q/27giOLOxkFOc21iTCWaRiaduuplYMSV4Ag3P3Sv0z/NKC3lDDFHOAsqQN2Y tCIPFCESKwNhLrG6U1Be5mE2CHvloJsjuhmCLwYeVw391NRDcBLrQ1I2+LPfV+9Pbb0Z Ord4tToscK3neksr0udmopVXm3k72axs+DHCHr3Njo4FCp2VaUGnSvy7WlOD5E8+57+r Nrx/Oq6vaXiibE0PqHMyLDsHfvk4MHJRSw51vCLN9zWNAS0c4iQvD8C0aj+MxSK19+uW F6+sGr3eFUh9iwSvZFXbWJRogN5S8aiBtsW5RH7xa1SVqx4VJtWHUaWPSm4awNVnkGH3 zg3g== X-Gm-Message-State: AOAM530NxYDJQbAKC68ZbcfQxVb6N2VK9/nygxKqW1nLbrhsaaSRq7TQ XeZZwWTb51E/U0orcrYYBu8z+geQ9Ke14HYa7ZL9PeHOh23HPJ3U71sXQlnAdpEb/EsjtL1eGyD NZbawirkmF28QFF+xkaVoj6Es2Vqh9voOSTRpBmo7dtZcOiWXdDT7xLYujuCu/mAlanHoYblY5l M9DEmZvw== X-Google-Smtp-Source: ABdhPJy6Vyr3Yml1glQmrfLDGPwyddcpi+Twx07WwFVSKFLE5+Zv/pDSG1CKAyUwCo1VusyPpIjAUQ== X-Received: by 2002:a17:90a:2ec6:: with SMTP id h6mr11282529pjs.103.1622726150998; Thu, 03 Jun 2021 06:15:50 -0700 (PDT) Received: from dev01.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id t24sm2336917pji.56.2021.06.03.06.15.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 06:15:50 -0700 (PDT) From: Devesh Sharma To: linux-rdma@vger.kernel.org Cc: Devesh Sharma Subject: [PATCH V7 for-next 1/3] RDMA/bnxt_re: Enable global atomic ops if platform supports Date: Thu, 3 Jun 2021 18:45:32 +0530 Message-Id: <20210603131534.982257-2-devesh.sharma@broadcom.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210603131534.982257-1-devesh.sharma@broadcom.com> References: <20210603131534.982257-1-devesh.sharma@broadcom.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-rdma@vger.kernel.org Enabling Atomic operations for Gen P5 devices if the underlying platform supports global atomic ops. Signed-off-by: Devesh Sharma --- drivers/infiniband/hw/bnxt_re/ib_verbs.c | 4 ++++ drivers/infiniband/hw/bnxt_re/main.c | 3 +++ drivers/infiniband/hw/bnxt_re/qplib_res.c | 17 +++++++++++++++++ drivers/infiniband/hw/bnxt_re/qplib_res.h | 1 + drivers/infiniband/hw/bnxt_re/qplib_sp.c | 13 ++++++++++++- drivers/infiniband/hw/bnxt_re/qplib_sp.h | 2 -- 6 files changed, 37 insertions(+), 3 deletions(-) diff --git a/drivers/infiniband/hw/bnxt_re/ib_verbs.c b/drivers/infiniband/hw/bnxt_re/ib_verbs.c index 537471ffaa79..a113d8d9e9ed 100644 --- a/drivers/infiniband/hw/bnxt_re/ib_verbs.c +++ b/drivers/infiniband/hw/bnxt_re/ib_verbs.c @@ -163,6 +163,10 @@ int bnxt_re_query_device(struct ib_device *ibdev, ib_attr->max_qp_init_rd_atom = dev_attr->max_qp_init_rd_atom; ib_attr->atomic_cap = IB_ATOMIC_NONE; ib_attr->masked_atomic_cap = IB_ATOMIC_NONE; + if (dev_attr->is_atomic) { + ib_attr->atomic_cap = IB_ATOMIC_GLOB; + ib_attr->masked_atomic_cap = IB_ATOMIC_GLOB; + } ib_attr->max_ee_rd_atom = 0; ib_attr->max_res_rd_atom = 0; diff --git a/drivers/infiniband/hw/bnxt_re/main.c b/drivers/infiniband/hw/bnxt_re/main.c index b090dfa4f4cb..0de4e22f9750 100644 --- a/drivers/infiniband/hw/bnxt_re/main.c +++ b/drivers/infiniband/hw/bnxt_re/main.c @@ -128,6 +128,9 @@ static int bnxt_re_setup_chip_ctx(struct bnxt_re_dev *rdev, u8 wqe_mode) rdev->rcfw.res = &rdev->qplib_res; bnxt_re_set_drv_mode(rdev, wqe_mode); + if (bnxt_qplib_determine_atomics(en_dev->pdev)) + ibdev_info(&rdev->ibdev, + "platform doesn't support global atomics."); return 0; } diff --git a/drivers/infiniband/hw/bnxt_re/qplib_res.c b/drivers/infiniband/hw/bnxt_re/qplib_res.c index 3ca47004b752..17f0701b3cee 100644 --- a/drivers/infiniband/hw/bnxt_re/qplib_res.c +++ b/drivers/infiniband/hw/bnxt_re/qplib_res.c @@ -959,3 +959,20 @@ int bnxt_qplib_alloc_res(struct bnxt_qplib_res *res, struct pci_dev *pdev, bnxt_qplib_free_res(res); return rc; } + +int bnxt_qplib_determine_atomics(struct pci_dev *dev) +{ + int comp; + u16 ctl2; + + comp = pci_enable_atomic_ops_to_root(dev, + PCI_EXP_DEVCAP2_ATOMIC_COMP32); + if (comp) + return -EOPNOTSUPP; + comp = pci_enable_atomic_ops_to_root(dev, + PCI_EXP_DEVCAP2_ATOMIC_COMP64); + if (comp) + return -EOPNOTSUPP; + pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &ctl2); + return !(ctl2 & PCI_EXP_DEVCTL2_ATOMIC_REQ); +} diff --git a/drivers/infiniband/hw/bnxt_re/qplib_res.h b/drivers/infiniband/hw/bnxt_re/qplib_res.h index 7a1ab38b95da..d2aea52bd1d8 100644 --- a/drivers/infiniband/hw/bnxt_re/qplib_res.h +++ b/drivers/infiniband/hw/bnxt_re/qplib_res.h @@ -373,6 +373,7 @@ void bnxt_qplib_free_ctx(struct bnxt_qplib_res *res, int bnxt_qplib_alloc_ctx(struct bnxt_qplib_res *res, struct bnxt_qplib_ctx *ctx, bool virt_fn, bool is_p5); +int bnxt_qplib_determine_atomics(struct pci_dev *dev); static inline void bnxt_qplib_hwq_incr_prod(struct bnxt_qplib_hwq *hwq, u32 cnt) { diff --git a/drivers/infiniband/hw/bnxt_re/qplib_sp.c b/drivers/infiniband/hw/bnxt_re/qplib_sp.c index 049b3576302b..3d9259632eb3 100644 --- a/drivers/infiniband/hw/bnxt_re/qplib_sp.c +++ b/drivers/infiniband/hw/bnxt_re/qplib_sp.c @@ -54,6 +54,17 @@ const struct bnxt_qplib_gid bnxt_qplib_gid_zero = {{ 0, 0, 0, 0, 0, 0, 0, 0, /* Device */ +static bool bnxt_qplib_is_atomic_cap(struct bnxt_qplib_rcfw *rcfw) +{ + u16 pcie_ctl2 = 0; + + if (!bnxt_qplib_is_chip_gen_p5(rcfw->res->cctx)) + return false; + + pcie_capability_read_word(rcfw->pdev, PCI_EXP_DEVCTL2, &pcie_ctl2); + return (pcie_ctl2 & PCI_EXP_DEVCTL2_ATOMIC_REQ); +} + static void bnxt_qplib_query_version(struct bnxt_qplib_rcfw *rcfw, char *fw_ver) { @@ -162,7 +173,7 @@ int bnxt_qplib_get_dev_attr(struct bnxt_qplib_rcfw *rcfw, attr->tqm_alloc_reqs[i * 4 + 3] = *(++tqm_alloc); } - attr->is_atomic = false; + attr->is_atomic = bnxt_qplib_is_atomic_cap(rcfw); bail: bnxt_qplib_rcfw_free_sbuf(rcfw, sbuf); return rc; diff --git a/drivers/infiniband/hw/bnxt_re/qplib_sp.h b/drivers/infiniband/hw/bnxt_re/qplib_sp.h index bc228340684f..260104783691 100644 --- a/drivers/infiniband/hw/bnxt_re/qplib_sp.h +++ b/drivers/infiniband/hw/bnxt_re/qplib_sp.h @@ -42,8 +42,6 @@ #define BNXT_QPLIB_RESERVED_QP_WRS 128 -#define PCI_EXP_DEVCTL2_ATOMIC_REQ 0x0040 - struct bnxt_qplib_dev_attr { #define FW_VER_ARR_LEN 4 u8 fw_ver[FW_VER_ARR_LEN];