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Tue, 20 Jul 2021 08:18:43 +0000 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 20 Jul 2021 08:18:25 +0000 Received: from vdi.nvidia.com (172.20.187.5) by mail.nvidia.com (172.20.187.15) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 20 Jul 2021 01:18:22 -0700 From: Yishai Hadas To: CC: , , , , , Ido Kalir Subject: [PATCH rdma-core 23/27] pyverbs/mlx5: Wrap mlx5_cqe64 struct and add enums Date: Tue, 20 Jul 2021 11:16:43 +0300 Message-ID: <20210720081647.1980-24-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210720081647.1980-1-yishaih@nvidia.com> References: <20210720081647.1980-1-yishaih@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7a94a278-6d82-4df6-2941-08d94b56fd68 X-MS-TrafficTypeDiagnostic: BL0PR12MB2819: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1775; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jul 2021 08:18:43.8699 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7a94a278-6d82-4df6-2941-08d94b56fd68 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.35];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT068.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB2819 Precedence: bulk List-ID: X-Mailing-List: linux-rdma@vger.kernel.org From: Edward Srouji Add a Mlx5Cqe64 class that wraps mlx5_cqe64 C struct, and provide an easy way to users to get/set its fields. In addition expose related enums. Both are relevant and necessary for DevX data path. Reviewed-by: Ido Kalir Signed-off-by: Edward Srouji --- pyverbs/providers/mlx5/libmlx5.pxd | 14 +++++++ pyverbs/providers/mlx5/mlx5dv.pxd | 3 ++ pyverbs/providers/mlx5/mlx5dv.pyx | 71 +++++++++++++++++++++++++++++++++ pyverbs/providers/mlx5/mlx5dv_enums.pxd | 22 ++++++++++ 4 files changed, 110 insertions(+) diff --git a/pyverbs/providers/mlx5/libmlx5.pxd b/pyverbs/providers/mlx5/libmlx5.pxd index de4008d..af034ad 100644 --- a/pyverbs/providers/mlx5/libmlx5.pxd +++ b/pyverbs/providers/mlx5/libmlx5.pxd @@ -273,12 +273,26 @@ cdef extern from 'infiniband/mlx5dv.h': qp qp srq srq + cdef struct mlx5_cqe64: + uint16_t wqe_id + uint32_t imm_inval_pkey + uint32_t byte_cnt + uint64_t timestamp + uint16_t wqe_counter + uint8_t signature + uint8_t op_own + void mlx5dv_set_ctrl_seg(mlx5_wqe_ctrl_seg *seg, uint16_t pi, uint8_t opcode, uint8_t opmod, uint32_t qp_num, uint8_t fm_ce_se, uint8_t ds, uint8_t signature, uint32_t imm) void mlx5dv_set_data_seg(mlx5_wqe_data_seg *seg, uint32_t length, uint32_t lkey, uintptr_t address) + uint8_t mlx5dv_get_cqe_owner(mlx5_cqe64 *cqe) + void mlx5dv_set_cqe_owner(mlx5_cqe64 *cqe, uint8_t val) + uint8_t mlx5dv_get_cqe_se(mlx5_cqe64 *cqe) + uint8_t mlx5dv_get_cqe_format(mlx5_cqe64 *cqe) + uint8_t mlx5dv_get_cqe_opcode(mlx5_cqe64 *cqe) bool mlx5dv_is_supported(v.ibv_device *device) v.ibv_context* mlx5dv_open_device(v.ibv_device *device, mlx5dv_context_attr *attr) diff --git a/pyverbs/providers/mlx5/mlx5dv.pxd b/pyverbs/providers/mlx5/mlx5dv.pxd index 2b758fe..968cbdb 100644 --- a/pyverbs/providers/mlx5/mlx5dv.pxd +++ b/pyverbs/providers/mlx5/mlx5dv.pxd @@ -83,3 +83,6 @@ cdef class Mlx5DevxObj(PyverbsCM): cdef dv.mlx5dv_devx_obj *obj cdef Context context cdef object out_view + +cdef class Mlx5Cqe64(PyverbsObject): + cdef dv.mlx5_cqe64 *cqe diff --git a/pyverbs/providers/mlx5/mlx5dv.pyx b/pyverbs/providers/mlx5/mlx5dv.pyx index ab0bd4a..8d6bae0 100644 --- a/pyverbs/providers/mlx5/mlx5dv.pyx +++ b/pyverbs/providers/mlx5/mlx5dv.pyx @@ -1507,3 +1507,74 @@ cdef class Mlx5UMEM(PyverbsCM): def umem_addr(self): if self.addr: return self.addr + + +cdef class Mlx5Cqe64(PyverbsObject): + def __init__(self, addr): + self.cqe = addr + + def dump(self): + dump_format = '{:08x} {:08x} {:08x} {:08x}\n' + str = '' + for i in range(0, 16, 4): + str += dump_format.format(be32toh((self.cqe)[i]), + be32toh((self.cqe)[i + 1]), + be32toh((self.cqe)[i + 2]), + be32toh((self.cqe)[i + 3])) + return str + + def is_empty(self): + for i in range(16): + if be32toh((self.cqe)[i]) != 0: + return False + return True + + @property + def owner(self): + return dv.mlx5dv_get_cqe_owner(self.cqe) + @owner.setter + def owner(self, val): + dv.mlx5dv_set_cqe_owner(self.cqe, val) + + @property + def se(self): + return dv.mlx5dv_get_cqe_se(self.cqe) + + @property + def format(self): + return dv.mlx5dv_get_cqe_format(self.cqe) + + @property + def opcode(self): + return dv.mlx5dv_get_cqe_opcode(self.cqe) + + @property + def imm_inval_pkey(self): + return be32toh(self.cqe.imm_inval_pkey) + + @property + def wqe_id(self): + return be16toh(self.cqe.wqe_id) + + @property + def byte_cnt(self): + return be32toh(self.cqe.byte_cnt) + + @property + def timestamp(self): + return be64toh(self.cqe.timestamp) + + @property + def wqe_counter(self): + return be16toh(self.cqe.wqe_counter) + + @property + def signature(self): + return self.cqe.signature + + @property + def op_own(self): + return self.cqe.op_own + + def __str__(self): + return (((self.cqe)[0])).__str__() diff --git a/pyverbs/providers/mlx5/mlx5dv_enums.pxd b/pyverbs/providers/mlx5/mlx5dv_enums.pxd index 9f8d1a1..60713e8 100644 --- a/pyverbs/providers/mlx5/mlx5dv_enums.pxd +++ b/pyverbs/providers/mlx5/mlx5dv_enums.pxd @@ -193,6 +193,28 @@ cdef extern from 'infiniband/mlx5dv.h': MLX5DV_OBJ_AH MLX5DV_OBJ_PD + cpdef enum: + MLX5_RCV_DBR + MLX5_SND_DBR + + cpdef enum: + MLX5_CQE_OWNER_MASK + MLX5_CQE_REQ + MLX5_CQE_RESP_WR_IMM + MLX5_CQE_RESP_SEND + MLX5_CQE_RESP_SEND_IMM + MLX5_CQE_RESP_SEND_INV + MLX5_CQE_RESIZE_CQ + MLX5_CQE_NO_PACKET + MLX5_CQE_SIG_ERR + MLX5_CQE_REQ_ERR + MLX5_CQE_RESP_ERR + MLX5_CQE_INVALID + + cpdef enum: + MLX5_SEND_WQE_BB + MLX5_SEND_WQE_SHIFT + cpdef unsigned long long MLX5DV_RES_TYPE_QP cpdef unsigned long long MLX5DV_RES_TYPE_RWQ cpdef unsigned long long MLX5DV_RES_TYPE_DBR