From patchwork Wed Sep 7 23:36:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Saeed Mahameed X-Patchwork-Id: 12969470 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89A14ECAAD3 for ; Wed, 7 Sep 2022 23:37:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230112AbiIGXhU (ORCPT ); Wed, 7 Sep 2022 19:37:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53010 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230031AbiIGXhP (ORCPT ); Wed, 7 Sep 2022 19:37:15 -0400 Received: from sin.source.kernel.org (sin.source.kernel.org [145.40.73.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2F7527C1CF; Wed, 7 Sep 2022 16:37:13 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id 6A008CE1E05; Wed, 7 Sep 2022 23:37:12 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 95474C433D7; Wed, 7 Sep 2022 23:37:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1662593830; bh=Xy/P04BxUZSe9boIeJFProSOXcQrLF/gu7yicfUSKlY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cbqHrQB8DN1dSafiw5lAUFS8i+GnFOIpjHqntRGihFWiDBlgHWhceYVLKYlrpan16 /RMnrQdlbLDKtoU5xAneeblEW6q9xrRIX3LDrrEn1lpBJRZBfDQBRGyZ+rcdzmBE9N Zxo0Zky33YXNTPi6UfDl0bB6vBE5WMYShKS3NaorTZO4XmUV3C1EzWdkmICo3+SYVH HNa+SGxzVLw6M5bybRmaYem79lVQXrq7ZrWGtKbp8+5okAq6RnpSL8rqyzTokQAaS4 1NxYNsRdNhJ2t0Losu1IACdkbIb4qMcS9yb9+GqfG7BR4KOLjCPdq+iZ87f3i541Yy BA3GP7diRfu1A== From: Saeed Mahameed To: Saeed Mahameed , Leon Romanovsky Cc: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , netdev@vger.kernel.org, Tariq Toukan , Jason Gunthorpe , linux-rdma@vger.kernel.org, Aya Levin , Eran Ben Elisha Subject: [PATCH mlx5-next 01/14] net/mlx5: Expose NPPS related registers Date: Wed, 7 Sep 2022 16:36:23 -0700 Message-Id: <20220907233636.388475-2-saeed@kernel.org> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220907233636.388475-1-saeed@kernel.org> References: <20220907233636.388475-1-saeed@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-rdma@vger.kernel.org From: Aya Levin Add management capability bits indicating firmware may support N pulses per second. Add corresponding fields in MTPPS register. Signed-off-by: Aya Levin Reviewed-by: Eran Ben Elisha Signed-off-by: Saeed Mahameed --- include/linux/mlx5/mlx5_ifc.h | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index 4acd5610e96b..e2f71c8d9bd7 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -9789,7 +9789,9 @@ struct mlx5_ifc_pcam_reg_bits { struct mlx5_ifc_mcam_enhanced_features_bits { u8 reserved_at_0[0x5d]; u8 mcia_32dwords[0x1]; - u8 reserved_at_5e[0xc]; + u8 out_pulse_duration_ns[0x1]; + u8 npps_period[0x1]; + u8 reserved_at_60[0xa]; u8 reset_state[0x1]; u8 ptpcyc2realtime_modify[0x1]; u8 reserved_at_6c[0x2]; @@ -10289,7 +10291,12 @@ struct mlx5_ifc_mtpps_reg_bits { u8 reserved_at_18[0x4]; u8 cap_max_num_of_pps_out_pins[0x4]; - u8 reserved_at_20[0x24]; + u8 reserved_at_20[0x13]; + u8 cap_log_min_npps_period[0x5]; + u8 reserved_at_38[0x3]; + u8 cap_log_min_out_pulse_duration_ns[0x5]; + + u8 reserved_at_40[0x4]; u8 cap_pin_3_mode[0x4]; u8 reserved_at_48[0x4]; u8 cap_pin_2_mode[0x4]; @@ -10308,7 +10315,9 @@ struct mlx5_ifc_mtpps_reg_bits { u8 cap_pin_4_mode[0x4]; u8 field_select[0x20]; - u8 reserved_at_a0[0x60]; + u8 reserved_at_a0[0x20]; + + u8 npps_period[0x40]; u8 enable[0x1]; u8 reserved_at_101[0xb]; @@ -10317,7 +10326,8 @@ struct mlx5_ifc_mtpps_reg_bits { u8 pin_mode[0x4]; u8 pin[0x8]; - u8 reserved_at_120[0x20]; + u8 reserved_at_120[0x2]; + u8 out_pulse_duration_ns[0x1e]; u8 time_stamp[0x40];