From patchwork Mon Jul 17 12:04:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ilpo_J=C3=A4rvinen?= X-Patchwork-Id: 13315547 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81B3CEB64DC for ; Mon, 17 Jul 2023 12:07:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230449AbjGQMHS (ORCPT ); Mon, 17 Jul 2023 08:07:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40552 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231184AbjGQMHP (ORCPT ); Mon, 17 Jul 2023 08:07:15 -0400 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F65810E4; Mon, 17 Jul 2023 05:06:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689595609; x=1721131609; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=32kRKfdMgDzPzA7zG83cMwuqvw0HkhDshGCOND8kKRk=; b=cLNXM8HVveJmjjSca+UcMMTJr4JrX8zXGbXCLtVlWVmrdcKa2J1+uMu3 APQZ0opFu2faKy5HomRcwvU1n1AFrjeOEbnnrpOUcK4Z5BU7TDmLEt3q/ e/L9xSJcbQHwscBwxM3on8/WN7e3rsV3R/gs7JFYio5EdUq9QORSnW31N yRSjAb08G6aT9zHzUuT4MUfDFsGoIQRz21e0CZOnMfnI7mddLNZ+m2/Mx 3PfoU0KVMtHDbqAeoTg4KkGBGilr3ARkfdUK2sxMDDqWy2CP8a15qqIzq OQ0qY2hBLqajtU6NEx8wKzCF3cO7xZqnoJicH6cmX8qF9gYvhL4Z8l+VP w==; X-IronPort-AV: E=McAfee;i="6600,9927,10773"; a="432081825" X-IronPort-AV: E=Sophos;i="6.01,211,1684825200"; d="scan'208";a="432081825" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jul 2023 05:06:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10773"; a="752876275" X-IronPort-AV: E=Sophos;i="6.01,211,1684825200"; d="scan'208";a="752876275" Received: from dkravtso-mobl1.ccr.corp.intel.com (HELO ijarvine-mobl2.ger.corp.intel.com) ([10.252.45.233]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jul 2023 05:06:34 -0700 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Emmanuel Grumbach , "Rafael J . Wysocki" , Heiner Kallweit , Lukas Wunner , Andy Shevchenko , Saeed Mahameed , Leon Romanovsky , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Moshe Shemesh , netdev@vger.kernel.org, linux-rdma@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Dean Luick , =?utf-8?q?Jonas_Dre=C3=9Fl?= =?utf-8?q?er?= , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Moshe Shemesh , Simon Horman , stable@vger.kernel.org Subject: [PATCH v5 07/11] net/mlx5: Use RMW accessors for changing LNKCTL Date: Mon, 17 Jul 2023 15:04:59 +0300 Message-Id: <20230717120503.15276-8-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230717120503.15276-1-ilpo.jarvinen@linux.intel.com> References: <20230717120503.15276-1-ilpo.jarvinen@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-rdma@vger.kernel.org Don't assume that only the driver would be accessing LNKCTL of the upstream bridge. ASPM policy changes can trigger write to LNKCTL outside of driver's control. Use RMW capability accessors which do proper locking to avoid losing concurrent updates to the register value. Fixes: eabe8e5e88f5 ("net/mlx5: Handle sync reset now event") Suggested-by: Lukas Wunner Signed-off-by: Ilpo Järvinen Reviewed-by: Moshe Shemesh Reviewed-by: Simon Horman Cc: stable@vger.kernel.org --- drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c b/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c index 4804990b7f22..99dcbd006357 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c @@ -384,16 +384,11 @@ static int mlx5_pci_link_toggle(struct mlx5_core_dev *dev) pci_cfg_access_lock(sdev); } /* PCI link toggle */ - err = pci_read_config_word(bridge, cap + PCI_EXP_LNKCTL, ®16); - if (err) - return err; - reg16 |= PCI_EXP_LNKCTL_LD; - err = pci_write_config_word(bridge, cap + PCI_EXP_LNKCTL, reg16); + err = pcie_capability_set_word(bridge, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_LD); if (err) return err; msleep(500); - reg16 &= ~PCI_EXP_LNKCTL_LD; - err = pci_write_config_word(bridge, cap + PCI_EXP_LNKCTL, reg16); + err = pcie_capability_clear_word(bridge, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_LD); if (err) return err;