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Wed, 4 Sep 2024 08:30:58 -0700 From: Michael Guralnik To: , CC: , , , Michael Guralnik Subject: [PATCH rdma-next 8/8] net/mlx5: Handle memory scheme ODP capabilities Date: Wed, 4 Sep 2024 18:30:38 +0300 Message-ID: <20240904153038.23054-9-michaelgur@nvidia.com> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20240904153038.23054-1-michaelgur@nvidia.com> References: <20240904153038.23054-1-michaelgur@nvidia.com> Precedence: bulk X-Mailing-List: linux-rdma@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001EA:EE_|SJ2PR12MB8882:EE_ X-MS-Office365-Filtering-Correlation-Id: 959928c0-e430-49cd-44bd-08dcccf69b09 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: WXaHF7D6eYS7fuBhOIk0U2gNlhkxTn8Gf521Y1K4CNQU17WuWFkjCLz3N+QCc4HWJAUAxdOpTrQojYAm7ELTni5AW1Jc0EDl35vQdjfRFfzkJB3BtQF/5yowXXJaucHO7xzjqOkiVAft8FR9YAMD1i4cdb2W8Bek7kDW4dRATOiL+8rfnY61kFAYrrfSKuhJsHmcto9eOdLffNSH1kqwiLUprTab2rBkbYaxLcg8KdgAgxGkRhqAv2Qp/0e2tMfwySSAlManXbVaUA67OqiaI8FeRbtODgEzZL6vPWRQA655fOBTvFDyeAylJKshvA0pPS8sHwfbJpqOSXeDe/8zelkty3BhiH5KyYfjgaOonv3Mabu/7qe4NO/qYM33Wc4AwiAE1GreITqvPYIJpd2fjbxuexGj/kcuQp91Z3Z5BndsKEExENyqbe4mcBkaXyfl1QTVPu+9jyx/neMrXBn3kb5VV8rhMExeiZEzu84aHoWC4qi2G+KisMaeiWLxgcHquTIj1nbSeVlmBAa3oS3KcXEh0H/HTUP3swM7olhK6v5yr9SMaOrAXhLQs81pFpyRfxtdzqAB55oxz1R+ESS+vSb+oSY6S+gyCm1dKYSWWts6EM3r9eIOsL2hIWS/9WttY1/JDSRmifj/9ngk3OPfyfOkiGti9qteji7xf7e1v7K1tqWCZ3GfumnwTTUsoW44IWk+oI6a4WXkOWPNsQnIfv1CJSImVHJv8tpiuEyi23L30v4+ok1o8tcESHxGO+tuKahEcKwYmY7z65ikV7GlFJ0krhMHbpOvK0Anacoe/L4vvsgseqh7rBPnyX/jvt+Z00XcXn9kOynVsti/YxQqtnnnN6HtYbmMXzZVVAakLKtzV6cHCduCRz6XycyIOKRD2yEfLQ1drAM+YstS2Ha4NNicrnLGOpUzDzNRbt5sMlr+/vDWCmztFeBsQENb6Li+qh8r/ytdpOF9uZpMhMMRSm4C4zFUotUfsp6K0tRY4ynHEPA1EUjXjEJ2Xfgtl2XDGkEJjq5KuQPHaANdFqItqj9rm6pnlnvgn0nLgfoWNtQBVNSwKDNelLmQCfYhzGirymcxNOPUgIAwXMVi/yqABqY0c4BsQXIZIccPn4l8976Q728W3yppB+GhaAz9HpcHryET4v18NX1EeQ64NmhDiQ4RjrLgiFMISogMR1z18HMrUpczHrXxBw0WYfIkimiD6xp/61JXQq2XMBMyx+mxxaQeO/pgg2Ea8y/v2IRbqyqY+gZNSOQ0gPe0fyQfEJLhZe8oDiC0+te+WSbqUsvuLic+oSWnXEg7bA2ptJr9IRA/mECPrrZtUgzV4Umga7nHm+RWsQ2TaSvBtKEi8xBbrMMbL1kPZG+Q+Fx6aCgrfqEJb6LBQrOqRQJCVq+fqi/9QWqgXuYbc7O/KT66qzRbI+89DNuDCUwrcdK8kEjyJzznIw7KPMHVo+bIcu3gwHiV X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2024 15:31:11.3614 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 959928c0-e430-49cd-44bd-08dcccf69b09 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001EA.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8882 When running over new FW that supports the new memory scheme ODP, set the cap in the FW to signal the FW we are working in the new scheme. In the memory scheme ODP the per_transport_service capabilities are RO for the driver so we skip their setting. Signed-off-by: Michael Guralnik Reviewed-by: Leon Romanovsky --- .../net/ethernet/mellanox/mlx5/core/main.c | 22 +++++++++++++++---- include/linux/mlx5/device.h | 10 ++++++--- 2 files changed, 25 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/ethernet/mellanox/mlx5/core/main.c index cc2aa46cff04..944c209e9569 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/main.c @@ -454,8 +454,8 @@ static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx) static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx) { + bool do_set = false, mem_page_fault = false; void *set_hca_cap; - bool do_set = false; int err; if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) || @@ -470,6 +470,17 @@ static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx) memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ODP]->cur, MLX5_ST_SZ_BYTES(odp_cap)); + /* For best performance, enable memory scheme ODP only when + * it has page prefetch enabled. + */ + if (MLX5_CAP_ODP_MAX(dev, mem_page_fault) && + MLX5_CAP_ODP_MAX(dev, memory_page_fault_scheme_cap.page_prefetch)) { + mem_page_fault = true; + do_set = true; + MLX5_SET(odp_cap, set_hca_cap, mem_page_fault, mem_page_fault); + goto set; + }; + #define ODP_CAP_SET_MAX(dev, field) \ do { \ u32 _res = MLX5_CAP_ODP_MAX(dev, field); \ @@ -494,10 +505,13 @@ static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx) ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.read); ODP_CAP_SET_MAX(dev, transport_page_fault_scheme_cap.dc_odp_caps.atomic); - if (!do_set) - return 0; +set: + if (do_set) + err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP); - return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP); + mlx5_core_dbg(dev, "Using ODP %s scheme\n", + mem_page_fault ? "memory" : "transport"); + return err; } static int max_uc_list_get_devlink_param(struct mlx5_core_dev *dev) diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h index 154095256d0d..57c9b18c3adb 100644 --- a/include/linux/mlx5/device.h +++ b/include/linux/mlx5/device.h @@ -1389,9 +1389,13 @@ enum mlx5_qcam_feature_groups { #define MLX5_CAP_ODP(mdev, cap)\ MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, cap) -#define MLX5_CAP_ODP_SCHEME(mdev, cap) \ - MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, \ - transport_page_fault_scheme_cap.cap) +#define MLX5_CAP_ODP_SCHEME(mdev, cap) \ + (MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, \ + mem_page_fault) ? \ + MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, \ + memory_page_fault_scheme_cap.cap) : \ + MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, \ + transport_page_fault_scheme_cap.cap)) #define MLX5_CAP_ODP_MAX(mdev, cap)\ MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->max, cap)