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Mon, 9 Sep 2024 03:05:08 -0700 From: Michael Guralnik To: , CC: , , , Michael Guralnik Subject: [PATCH v2 rdma-next 1/8] net/mlx5: Expand mkey page size to support 6 bits Date: Mon, 9 Sep 2024 13:04:57 +0300 Message-ID: <20240909100504.29797-2-michaelgur@nvidia.com> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20240909100504.29797-1-michaelgur@nvidia.com> References: <20240909100504.29797-1-michaelgur@nvidia.com> Precedence: bulk X-Mailing-List: linux-rdma@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9DC:EE_|SA3PR12MB9180:EE_ X-MS-Office365-Filtering-Correlation-Id: 785f5019-862b-4a0f-9c27-08dcd0b6eb1a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: IQVgEqm97zcFIxfVkCCn3OC/i1SXMgZspVpoVw21Lr1D7HtzgE/aszDrxggBp2TlRyXRhf2iJWmgWKzYgDQZQFsxsonL1Fh357PzLmB2CklRk4y16zCsOJwXO0gWC6Ul5ullrV5Mtte337CcS84pyy/ZU9jYHGC6LOmPkif2ffsyYTOlnj5IKLxUYF3uWqEbZo2xO+3S28BV7sweJCPxrERxXmhVTuk6N39MaKfXY5UZ7IvbdeieIBEFk/5O/3JD5h7aorw01rwr8KyCCq/xArMkXxe+d5HjA5KxXCV0RJDIZqOnq2SH4MZe6LcVZLqcv1+BGVECWJFPxsbTm8VO36bihl71/8lmojRLoAxnibQphe8VMhJa1sPwWO5wSW9Qls+cBsGr9gdAsgsn6B8xNrcwOb/WHdF1Nl1WpKPu9NRUTp4ElK3AwCvKIEHM4Tgyc2GtCh3rusmMKb2HyJ12WktkUG5Eo5VO/Q03LX540BuX3wmhtcEk9XUTgPICDZuB3vhftJI147q48spfiiFUJO3P0peUk3jLi/L8bevQHpVD6pAToO1dyvqRGv4aVSihd7QL5o5Aryb/00TXYNLAAwkSbRqfXA94MmAnkoMdGit2uCWxo8z52LV3Q3qHNb8+hNxIfDTzkjekZNWacR6o4R1ojOc0gRSIopzbN/a3YFyjJNZf59IAxt0miPHunAINr4wFRizvGD34XB8bAV1Ugv++UTLsI6t7kFzUQnTNjfzAeTAnJ+VRLoSR4UqhnhNuXkBDQgS4yFaCXjHe1IPoKOps8J/6xE+vEh3wzuWZAeiRopaJju0YS6w+5ZP62PG7a2lKyCqoboBuOXpCyihJ/T4xCA3F3/9U/BHXdgtbXTdRnxzMk4TZM7CHAoPQKaDz9JsYS6qIUCQwDodP8F8gTwn2ffFa8no9KdnuB+YaV0EsvgJcNvScsmi4risNsI/V/CkTa0NH0/vrLzsWmOfgzibH72QtGHcBKW7qPsILj5WLrdTbfHNRyrNLQeLgCj83LeQrUcgb+k2CZ/GsMwU5/YNuRW4A4ttdLqV97aLoQKQ3UwRYb68Gz6KEkIpoTmoz9f8hL1rAwCC5VLGXgU5B3U87jOmTxVqlkPt6YD9S/xEizcPZE5SZnGgUUbUWtUy+YvJgK5++EKPiIQ3CdG4zFB2ZOUOss94ttHgfRch+qQopTKiexowF/Qk+A2nmbp71Bb3neY6SAqS9MdVQxkcvh8vOGvX8O8vfRQmX+qQBaiJeIx3OlNv6S3VzD6DyyJ7lgMfu+ugjaIEXLx69O3ISLUGo+f60wqpAW4zJ7nINiAce9dBqCQO2RDLrjEZ84yaJi2ZCQIbmphNX8PhPE72A3Uo1WzPGf3NYgANVrBo5AifS1e+i2ahIhIi9JNnGuFc6TyS/zB1NeiT4byKpclveOL+f5g1MeJV8e7m3pLuw2/RNfX7ta8DnEeJ8+5IURS3F X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Sep 2024 10:05:22.5845 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 785f5019-862b-4a0f-9c27-08dcd0b6eb1a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9DC.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB9180 Protect the usage of the 6th bit with the relevant capability to ensure we are using the new page sizes with FW that supports the bit extension. Signed-off-by: Michael Guralnik Reviewed-by: Leon Romanovsky --- drivers/infiniband/hw/mlx5/mlx5_ib.h | 27 ++++++++++++++++----------- drivers/infiniband/hw/mlx5/mr.c | 10 ++++------ drivers/infiniband/hw/mlx5/odp.c | 2 +- include/linux/mlx5/mlx5_ifc.h | 7 ++++--- 4 files changed, 25 insertions(+), 21 deletions(-) diff --git a/drivers/infiniband/hw/mlx5/mlx5_ib.h b/drivers/infiniband/hw/mlx5/mlx5_ib.h index 926a965e4570..ea8eb368108f 100644 --- a/drivers/infiniband/hw/mlx5/mlx5_ib.h +++ b/drivers/infiniband/hw/mlx5/mlx5_ib.h @@ -63,17 +63,6 @@ __mlx5_log_page_size_to_bitmap(unsigned int log_pgsz_bits, return GENMASK(largest_pg_shift, pgsz_shift); } -/* - * For mkc users, instead of a page_offset the command has a start_iova which - * specifies both the page_offset and the on-the-wire IOVA - */ -#define mlx5_umem_find_best_pgsz(umem, typ, log_pgsz_fld, pgsz_shift, iova) \ - ib_umem_find_best_pgsz(umem, \ - __mlx5_log_page_size_to_bitmap( \ - __mlx5_bit_sz(typ, log_pgsz_fld), \ - pgsz_shift), \ - iova) - static __always_inline unsigned long __mlx5_page_offset_to_bitmask(unsigned int page_offset_bits, unsigned int offset_shift) @@ -1725,4 +1714,20 @@ static inline u32 smi_to_native_portnum(struct mlx5_ib_dev *dev, u32 port) return (port - 1) / dev->num_ports + 1; } +/* + * For mkc users, instead of a page_offset the command has a start_iova which + * specifies both the page_offset and the on-the-wire IOVA + */ +static __always_inline unsigned long +mlx5_umem_mkc_find_best_pgsz(struct mlx5_ib_dev *dev, struct ib_umem *umem, + u64 iova) +{ + int page_size_bits = + MLX5_CAP_GEN_2(dev->mdev, umr_log_entity_size_5) ? 6 : 5; + unsigned long bitmap = + __mlx5_log_page_size_to_bitmap(page_size_bits, 0); + + return ib_umem_find_best_pgsz(umem, bitmap, iova); +} + #endif /* MLX5_IB_H */ diff --git a/drivers/infiniband/hw/mlx5/mr.c b/drivers/infiniband/hw/mlx5/mr.c index 73962bd0b216..3d6a14ece6db 100644 --- a/drivers/infiniband/hw/mlx5/mr.c +++ b/drivers/infiniband/hw/mlx5/mr.c @@ -1119,8 +1119,7 @@ static struct mlx5_ib_mr *alloc_cacheable_mr(struct ib_pd *pd, if (umem->is_dmabuf) page_size = mlx5_umem_dmabuf_default_pgsz(umem, iova); else - page_size = mlx5_umem_find_best_pgsz(umem, mkc, log_page_size, - 0, iova); + page_size = mlx5_umem_mkc_find_best_pgsz(dev, umem, iova); if (WARN_ON(!page_size)) return ERR_PTR(-EINVAL); @@ -1425,8 +1424,8 @@ static struct ib_mr *create_real_mr(struct ib_pd *pd, struct ib_umem *umem, mr = alloc_cacheable_mr(pd, umem, iova, access_flags, MLX5_MKC_ACCESS_MODE_MTT); } else { - unsigned int page_size = mlx5_umem_find_best_pgsz( - umem, mkc, log_page_size, 0, iova); + unsigned int page_size = + mlx5_umem_mkc_find_best_pgsz(dev, umem, iova); mutex_lock(&dev->slow_path_mutex); mr = reg_create(pd, umem, iova, access_flags, page_size, @@ -1744,8 +1743,7 @@ static bool can_use_umr_rereg_pas(struct mlx5_ib_mr *mr, if (!mlx5r_umr_can_load_pas(dev, new_umem->length)) return false; - *page_size = - mlx5_umem_find_best_pgsz(new_umem, mkc, log_page_size, 0, iova); + *page_size = mlx5_umem_mkc_find_best_pgsz(dev, new_umem, iova); if (WARN_ON(!*page_size)) return false; return (mr->mmkey.cache_ent->rb_key.ndescs) >= diff --git a/drivers/infiniband/hw/mlx5/odp.c b/drivers/infiniband/hw/mlx5/odp.c index 44a3428ea342..221820874e7a 100644 --- a/drivers/infiniband/hw/mlx5/odp.c +++ b/drivers/infiniband/hw/mlx5/odp.c @@ -693,7 +693,7 @@ static int pagefault_dmabuf_mr(struct mlx5_ib_mr *mr, size_t bcnt, struct ib_umem_dmabuf *umem_dmabuf = to_ib_umem_dmabuf(mr->umem); u32 xlt_flags = 0; int err; - unsigned int page_size; + unsigned long page_size; if (flags & MLX5_PF_FLAGS_ENABLE) xlt_flags |= MLX5_IB_UPD_XLT_ENABLE; diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index 691a285f9c1e..1be2495362ee 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -1995,7 +1995,9 @@ struct mlx5_ifc_cmd_hca_cap_2_bits { u8 dp_ordering_force[0x1]; u8 reserved_at_89[0x9]; u8 query_vuid[0x1]; - u8 reserved_at_93[0xd]; + u8 reserved_at_93[0x5]; + u8 umr_log_entity_size_5[0x1]; + u8 reserved_at_99[0x7]; u8 max_reformat_insert_size[0x8]; u8 max_reformat_insert_offset[0x8]; @@ -4221,8 +4223,7 @@ struct mlx5_ifc_mkc_bits { u8 reserved_at_1c0[0x19]; u8 relaxed_ordering_read[0x1]; - u8 reserved_at_1d9[0x1]; - u8 log_page_size[0x5]; + u8 log_page_size[0x6]; u8 reserved_at_1e0[0x20]; };