From patchwork Fri Mar 2 09:23:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 10253917 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8523D6037F for ; Fri, 2 Mar 2018 09:26:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7E930288FD for ; Fri, 2 Mar 2018 09:26:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7337528926; Fri, 2 Mar 2018 09:26:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CE6DD288FD for ; Fri, 2 Mar 2018 09:26:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1425653AbeCBJYi (ORCPT ); Fri, 2 Mar 2018 04:24:38 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:49066 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1425472AbeCBJYR (ORCPT ); Fri, 2 Mar 2018 04:24:17 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 648A2607B9; Fri, 2 Mar 2018 09:24:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1519982656; bh=f2Ys1Tp4ktSMMJTJPqU2jjiYrfLiTpjrg6egyf0RlxY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lcjh46qqTlw6c01pbHaJgAbRbN5zE0pxGAEKeJDRDHa20YA2MrV1y0SthUAhFJOE8 nBAuoHxwLSGQSI2Q1Iy+Uvwbr8AG/BI7Gp2u9/ttK3Jr3tcdkonj2P3TPKHhxwo9fy LLdCNp0ktq4uUuj1jhr7mQnp4k9pGAwKVE9I3uEI= Received: from blr-ubuntu-87.qualcomm.com (blr-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.18.19]) (using TLSv1.1 with cipher ECDHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: sibis@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 17796602B8; Fri, 2 Mar 2018 09:24:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1519982655; bh=f2Ys1Tp4ktSMMJTJPqU2jjiYrfLiTpjrg6egyf0RlxY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hrafGzTe6PXHNNWYRpcxCzRW3thfvWAUUpZd/3FqCe0nevYw8R0ntDw0uoEHW8wiS gJFm5xuFVEawEz4487HiGaMjsEVMBJuIsz23liMa9dTIPZo/7ErEsO/VVkLMqAQhXQ B3d7NpGyR6TtLzc0Vf4CRNhnkClrHgDzOeJQc0Uw= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 17796602B8 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=sibis@codeaurora.org From: sibis To: bjorn.andersson@linaro.org Cc: linux-remoteproc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, sibis@codeaurora.org, georgi.djakov@linaro.org, jassisinghbrar@gmail.com, p.zabel@pengutronix.de, ohad@wizery.com, mark.rutland@arm.com, robh+dt@kernel.org, kyan@codeaurora.org, sricharan@codeaurora.org, akdwived@codeaurora.org, linux-arm-msm@vger.kernel.org Subject: [PATCH 1/6] reset: qcom: AOSS (Always on subsystem) reset controller Date: Fri, 2 Mar 2018 14:53:34 +0530 Message-Id: <1519982619-28336-2-git-send-email-sibis@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1519982619-28336-1-git-send-email-sibis@codeaurora.org> References: <1519982619-28336-1-git-send-email-sibis@codeaurora.org> Sender: linux-remoteproc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add reset controller driver for Qualcomm SDM845 SoC to control reset signals provided by AOSS for Modem, Venus ADSP, GPU, Camera, Wireless, Display subsystem Signed-off-by: sibis --- .../devicetree/bindings/reset/qcom,aoss-reset.txt | 54 +++++++ drivers/reset/Kconfig | 10 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-qcom-aoss.c | 161 +++++++++++++++++++++ include/dt-bindings/reset/qcom,aoss-sdm845.h | 17 +++ 5 files changed, 243 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt create mode 100644 drivers/reset/reset-qcom-aoss.c create mode 100644 include/dt-bindings/reset/qcom,aoss-sdm845.h diff --git a/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt new file mode 100644 index 0000000..5318e14 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt @@ -0,0 +1,54 @@ +Qualcomm AOSS Reset Controller +====================================== + +This binding describes a reset-controller found on AOSS (Always on SubSysem) +for Qualcomm SDM845 SoCs. + +Required properties: +- compatible: + Usage: required + Value type: + Definition: must be: + "qcom,aoss-reset-sdm845", "syscon" + +- reg: + Usage: required + Value type: + Definition: must specify the base address and size of the + syscon device. + + +- #reset-cells: + Usage: required + Value type: + Definition: must be 1; cell entry represents the reset index. + +example: + +aoss_reset: qcom,reset-controller@b2e0100 { + compatible = "qcom,aoss-reset-sdm845", "syscon"; + reg = <0xc2b0000 0x20004>; + #reset-cells = <1>; +}; + + +Specifying reset lines connected to IP modules +============================================== + +Device nodes that need access to reset lines should +specify them as a reset phandle in their corresponding node as +specified in reset.txt. + +Example: + + modem-pil@4080000 { + ... + + resets = <&aoss_reset AOSS_CC_MSS_RESTART>; + reset-names = "mss_restart"; + + ... + }; + +For list of all valid reset indicies see + diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 7fc7769..4b1da86 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -81,6 +81,16 @@ config RESET_PISTACHIO help This enables the reset driver for ImgTec Pistachio SoCs. +config RESET_QCOM_AOSS + bool "Qcom AOSS Reset Driver" + depends on ARCH_QCOM || COMPILE_TEST + select MFD_SYSCON + help + This enables the AOSS (Always On SubSystem) reset driver + for Qcom SoCs. Say Y if you want to control reset signals + provided by AOSS for Modem, Venus, ADSP, GPU, Camera, + Wireless, Display subsystem. Otherwise, say N. + config RESET_SIMPLE bool "Simple Reset Controller Driver" if COMPILE_TEST default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 132c24f..c30044a 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o obj-$(CONFIG_RESET_MESON) += reset-meson.o obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o +obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o diff --git a/drivers/reset/reset-qcom-aoss.c b/drivers/reset/reset-qcom-aoss.c new file mode 100644 index 0000000..eb8c69b --- /dev/null +++ b/drivers/reset/reset-qcom-aoss.c @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include + +struct qcom_aoss_reset_map { + unsigned int reg; + u8 bit; +}; + +struct qcom_aoss_desc { + const struct regmap_config *config; + const struct qcom_aoss_reset_map *resets; + int delay; + size_t num_resets; +}; + +struct qcom_aoss_reset_data { + struct reset_controller_dev rcdev; + struct regmap *regmap; + const struct qcom_aoss_desc *desc; +}; + +static const struct regmap_config aoss_sdm845_regmap_config = { + .name = "aoss-reset", + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x20000, + .fast_io = true, +}; + +static const struct qcom_aoss_reset_map aoss_sdm845_resets[] = { + [AOSS_CC_MSS_RESTART] = { 0x0, 0 }, + [AOSS_CC_CAMSS_RESTART] = { 0x1000, 0 }, + [AOSS_CC_VENUS_RESTART] = { 0x2000, 0 }, + [AOSS_CC_GPU_RESTART] = { 0x3000, 0 }, + [AOSS_CC_DISPSS_RESTART] = { 0x4000, 0 }, + [AOSS_CC_WCSS_RESTART] = { 0x10000, 0 }, + [AOSS_CC_LPASS_RESTART] = { 0x20000, 0 }, +}; + +static const struct qcom_aoss_desc aoss_sdm845_desc = { + .config = &aoss_sdm845_regmap_config, + .resets = aoss_sdm845_resets, + /* Wait 6 32kHz sleep cycles for reset */ + .delay = 200, + .num_resets = ARRAY_SIZE(aoss_sdm845_resets), +}; + +static struct qcom_aoss_reset_data *to_qcom_aoss_reset_data( + struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct qcom_aoss_reset_data, rcdev); +} + +static int qcom_aoss_control_assert(struct reset_controller_dev *rcdev, + unsigned long idx) +{ + struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev); + const struct qcom_aoss_reset_map *map = &data->desc->resets[idx]; + + if (idx >= rcdev->nr_resets) + return -EINVAL; + + return regmap_update_bits(data->regmap, map->reg, + BIT(map->bit), BIT(map->bit)); +} + +static int qcom_aoss_control_deassert(struct reset_controller_dev *rcdev, + unsigned long idx) +{ + struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev); + const struct qcom_aoss_reset_map *map = &data->desc->resets[idx]; + + if (idx >= rcdev->nr_resets) + return -EINVAL; + + return regmap_update_bits(data->regmap, map->reg, BIT(map->bit), 0); +} + +static int qcom_aoss_control_reset(struct reset_controller_dev *rcdev, + unsigned long idx) +{ + struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev); + int ret; + + ret = rcdev->ops->assert(rcdev, idx); + if (ret) + return ret; + + udelay(data->desc->delay); + + ret = rcdev->ops->deassert(rcdev, idx); + if (ret) + return ret; + + return 0; +} + +static const struct reset_control_ops qcom_aoss_reset_ops = { + .reset = qcom_aoss_control_reset, + .assert = qcom_aoss_control_assert, + .deassert = qcom_aoss_control_deassert, +}; + +static int qcom_aoss_reset_probe(struct platform_device *pdev) +{ + struct qcom_aoss_reset_data *data; + struct device *dev = &pdev->dev; + const struct qcom_aoss_desc *desc; + + desc = of_device_get_match_data(&pdev->dev); + if (!desc) + return -EINVAL; + + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->desc = desc; + data->regmap = syscon_node_to_regmap(dev->of_node); + if (IS_ERR(data->regmap)) { + dev_err(dev, "Unable to get aoss-reset regmap"); + return PTR_ERR(data->regmap); + } + regmap_attach_dev(dev, data->regmap, desc->config); + + data->rcdev.owner = THIS_MODULE; + data->rcdev.ops = &qcom_aoss_reset_ops; + data->rcdev.nr_resets = desc->num_resets; + data->rcdev.of_node = pdev->dev.of_node; + + return devm_reset_controller_register(&pdev->dev, &data->rcdev); +} + +static const struct of_device_id qcom_aoss_reset_of_match[] = { + { .compatible = "qcom,aoss-reset-sdm845", .data = &aoss_sdm845_desc}, + {} +}; + +static struct platform_driver qcom_aoss_reset_driver = { + .probe = qcom_aoss_reset_probe, + .driver = { + .name = "qcom_aoss_reset", + .of_match_table = qcom_aoss_reset_of_match, + }, +}; + +builtin_platform_driver(qcom_aoss_reset_driver); + +MODULE_DESCRIPTION("Qualcomm AOSS Reset Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/include/dt-bindings/reset/qcom,aoss-sdm845.h b/include/dt-bindings/reset/qcom,aoss-sdm845.h new file mode 100644 index 0000000..e9b38fc --- /dev/null +++ b/include/dt-bindings/reset/qcom,aoss-sdm845.h @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_RESET_AOSS_SDM_845_H +#define _DT_BINDINGS_RESET_AOSS_SDM_845_H + +#define AOSS_CC_MSS_RESTART 0 +#define AOSS_CC_CAMSS_RESTART 1 +#define AOSS_CC_VENUS_RESTART 2 +#define AOSS_CC_GPU_RESTART 3 +#define AOSS_CC_DISPSS_RESTART 4 +#define AOSS_CC_WCSS_RESTART 5 +#define AOSS_CC_LPASS_RESTART 6 + +#endif