| Message ID | 1520243613-30393-2-git-send-email-sibis@codeaurora.org (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
On Mon, Mar 05, 2018 at 03:23:28PM +0530, sibis wrote: > Add reset controller driver for Qualcomm SDM845 SoC to > control reset signals provided by AOSS for Modem, Venus > ADSP, GPU, Camera, Wireless, Display subsystem > > Signed-off-by: sibis <sibis@codeaurora.org> Need a full name here. > --- > .../devicetree/bindings/reset/qcom,aoss-reset.txt | 54 ++++++++ Separate patch for bindings (with the header) please. > drivers/reset/Kconfig | 10 ++ > drivers/reset/Makefile | 1 + > drivers/reset/reset-qcom-aoss.c | 151 +++++++++++++++++++++ > include/dt-bindings/reset/qcom,aoss-sdm845.h | 17 +++ > 5 files changed, 233 insertions(+) > create mode 100644 Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt > create mode 100644 drivers/reset/reset-qcom-aoss.c > create mode 100644 include/dt-bindings/reset/qcom,aoss-sdm845.h > > diff --git a/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt > new file mode 100644 > index 0000000..5318e14 > --- /dev/null > +++ b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt > @@ -0,0 +1,54 @@ > +Qualcomm AOSS Reset Controller > +====================================== > + > +This binding describes a reset-controller found on AOSS (Always on SubSysem) > +for Qualcomm SDM845 SoCs. > + > +Required properties: > +- compatible: > + Usage: required > + Value type: <string> > + Definition: must be: > + "qcom,aoss-reset-sdm845", "syscon" Someone in QCom needs to go fix the order of all your downstream compatibles or review your bindings before sending upstream. The standard ordering is <vendor>,<soc>-<block>. Why syscon? The description is this is just a reset controller. > + > +- reg: > + Usage: required > + Value type: <prop-encoded-array> > + Definition: must specify the base address and size of the > + syscon device. > + > + > +- #reset-cells: > + Usage: required > + Value type: <uint> > + Definition: must be 1; cell entry represents the reset index. > + > +example: > + > +aoss_reset: qcom,reset-controller@b2e0100 { > + compatible = "qcom,aoss-reset-sdm845", "syscon"; > + reg = <0xc2b0000 0x20004>; > + #reset-cells = <1>; > +}; > + > + > +Specifying reset lines connected to IP modules > +============================================== > + > +Device nodes that need access to reset lines should > +specify them as a reset phandle in their corresponding node as > +specified in reset.txt. > + > +Example: > + > + modem-pil@4080000 { > + ... > + > + resets = <&aoss_reset AOSS_CC_MSS_RESTART>; > + reset-names = "mss_restart"; > + > + ... > + }; > + > +For list of all valid reset indicies see > +<dt-bindings/reset/qcom,aoss-sdm845.h> Put this before the example. -- To unsubscribe from this list: send the line "unsubscribe linux-remoteproc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Rob, Thanks for the review, will add the changes in v3 of the patch series On 03/08/2018 03:05 AM, Rob Herring wrote: > On Mon, Mar 05, 2018 at 03:23:28PM +0530, sibis wrote: >> Add reset controller driver for Qualcomm SDM845 SoC to >> control reset signals provided by AOSS for Modem, Venus >> ADSP, GPU, Camera, Wireless, Display subsystem >> >> Signed-off-by: sibis <sibis@codeaurora.org> > > Need a full name here. > Will correct it >> --- >> .../devicetree/bindings/reset/qcom,aoss-reset.txt | 54 ++++++++ > > Separate patch for bindings (with the header) please. > Will make a separate patch >> drivers/reset/Kconfig | 10 ++ >> drivers/reset/Makefile | 1 + >> drivers/reset/reset-qcom-aoss.c | 151 +++++++++++++++++++++ >> include/dt-bindings/reset/qcom,aoss-sdm845.h | 17 +++ >> 5 files changed, 233 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt >> create mode 100644 drivers/reset/reset-qcom-aoss.c >> create mode 100644 include/dt-bindings/reset/qcom,aoss-sdm845.h >> >> diff --git a/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt >> new file mode 100644 >> index 0000000..5318e14 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt >> @@ -0,0 +1,54 @@ >> +Qualcomm AOSS Reset Controller >> +====================================== >> + >> +This binding describes a reset-controller found on AOSS (Always on SubSysem) >> +for Qualcomm SDM845 SoCs. >> + >> +Required properties: >> +- compatible: >> + Usage: required >> + Value type: <string> >> + Definition: must be: >> + "qcom,aoss-reset-sdm845", "syscon" > > Someone in QCom needs to go fix the order of all your downstream > compatibles or review your bindings before sending upstream. The > standard ordering is <vendor>,<soc>-<block>. > Will correct it. > Why syscon? The description is this is just a reset controller. > syscon was needed in the compatible list due to using syscon_node_to_regmap in the reset driver but I guess since it is just a reset controller the correct thing to do be ioremap the reg space and do devm_regmap_init_mmio on it. Will remove syscon. >> + >> +- reg: >> + Usage: required >> + Value type: <prop-encoded-array> >> + Definition: must specify the base address and size of the >> + syscon device. >> + >> + >> +- #reset-cells: >> + Usage: required >> + Value type: <uint> >> + Definition: must be 1; cell entry represents the reset index. >> + >> +example: >> + >> +aoss_reset: qcom,reset-controller@b2e0100 { >> + compatible = "qcom,aoss-reset-sdm845", "syscon"; >> + reg = <0xc2b0000 0x20004>; >> + #reset-cells = <1>; >> +}; >> + >> + >> +Specifying reset lines connected to IP modules >> +============================================== >> + >> +Device nodes that need access to reset lines should >> +specify them as a reset phandle in their corresponding node as >> +specified in reset.txt. >> + >> +Example: >> + >> + modem-pil@4080000 { >> + ... >> + >> + resets = <&aoss_reset AOSS_CC_MSS_RESTART>; >> + reset-names = "mss_restart"; >> + >> + ... >> + }; >> + >> +For list of all valid reset indicies see >> +<dt-bindings/reset/qcom,aoss-sdm845.h> > > Put this before the example. > ok > -- > To unsubscribe from this list: send the line "unsubscribe linux-remoteproc" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html >
Sibi, One cosmetic comment below. On 3/9/2018 6:55 AM, Sibi S wrote: > + >>> +This binding describes a reset-controller found on AOSS (Always on >>> SubSysem) >>> +for Qualcomm SDM845 SoCs. S/SubSysem/Subsytem ---Trilok Soni -- To unsubscribe from this list: send the line "unsubscribe linux-remoteproc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Trilok, Thanks for the review. I will include it in the v3 patch series. On 03/10/2018 02:59 AM, Trilok Soni wrote: > Sibi, > > One cosmetic comment below. > > On 3/9/2018 6:55 AM, Sibi S wrote: >> + >>>> +This binding describes a reset-controller found on AOSS (Always on >>>> SubSysem) >>>> +for Qualcomm SDM845 SoCs. > > S/SubSysem/Subsytem > Will correct it > ---Trilok Soni > > >
diff --git a/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt new file mode 100644 index 0000000..5318e14 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt @@ -0,0 +1,54 @@ +Qualcomm AOSS Reset Controller +====================================== + +This binding describes a reset-controller found on AOSS (Always on SubSysem) +for Qualcomm SDM845 SoCs. + +Required properties: +- compatible: + Usage: required + Value type: <string> + Definition: must be: + "qcom,aoss-reset-sdm845", "syscon" + +- reg: + Usage: required + Value type: <prop-encoded-array> + Definition: must specify the base address and size of the + syscon device. + + +- #reset-cells: + Usage: required + Value type: <uint> + Definition: must be 1; cell entry represents the reset index. + +example: + +aoss_reset: qcom,reset-controller@b2e0100 { + compatible = "qcom,aoss-reset-sdm845", "syscon"; + reg = <0xc2b0000 0x20004>; + #reset-cells = <1>; +}; + + +Specifying reset lines connected to IP modules +============================================== + +Device nodes that need access to reset lines should +specify them as a reset phandle in their corresponding node as +specified in reset.txt. + +Example: + + modem-pil@4080000 { + ... + + resets = <&aoss_reset AOSS_CC_MSS_RESTART>; + reset-names = "mss_restart"; + + ... + }; + +For list of all valid reset indicies see +<dt-bindings/reset/qcom,aoss-sdm845.h> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 7fc7769..1141733 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -81,6 +81,16 @@ config RESET_PISTACHIO help This enables the reset driver for ImgTec Pistachio SoCs. +config RESET_QCOM_AOSS + bool "Qcom AOSS Reset Driver" + depends on ARCH_QCOM || COMPILE_TEST + select MFD_SYSCON + help + This enables the AOSS (Always On SubSystem) reset driver + for Qualcomm SDM845 SoCs. Say Y if you want to control + reset signals provided by AOSS for Modem, Venus, ADSP, + GPU, Camera, Wireless, Display subsystem. Otherwise, say N. + config RESET_SIMPLE bool "Simple Reset Controller Driver" if COMPILE_TEST default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 132c24f..c30044a 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o obj-$(CONFIG_RESET_MESON) += reset-meson.o obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o +obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o diff --git a/drivers/reset/reset-qcom-aoss.c b/drivers/reset/reset-qcom-aoss.c new file mode 100644 index 0000000..1f3e3e8 --- /dev/null +++ b/drivers/reset/reset-qcom-aoss.c @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 The Linux Foundation. All rights reserved. + */ + +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/reset-controller.h> +#include <linux/regmap.h> +#include <linux/of_device.h> +#include <dt-bindings/reset/qcom,aoss-sdm845.h> + +struct qcom_aoss_reset_map { + unsigned int reg; + u8 bit; +}; + +struct qcom_aoss_desc { + const struct regmap_config *config; + const struct qcom_aoss_reset_map *resets; + int delay; + size_t num_resets; +}; + +struct qcom_aoss_reset_data { + struct reset_controller_dev rcdev; + struct regmap *regmap; + const struct qcom_aoss_desc *desc; +}; + +static const struct regmap_config aoss_sdm845_regmap_config = { + .name = "aoss-reset", + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x20000, + .fast_io = true, +}; + +static const struct qcom_aoss_reset_map aoss_sdm845_resets[] = { + [AOSS_CC_MSS_RESTART] = { 0x0, 0 }, + [AOSS_CC_CAMSS_RESTART] = { 0x1000, 0 }, + [AOSS_CC_VENUS_RESTART] = { 0x2000, 0 }, + [AOSS_CC_GPU_RESTART] = { 0x3000, 0 }, + [AOSS_CC_DISPSS_RESTART] = { 0x4000, 0 }, + [AOSS_CC_WCSS_RESTART] = { 0x10000, 0 }, + [AOSS_CC_LPASS_RESTART] = { 0x20000, 0 }, +}; + +static const struct qcom_aoss_desc aoss_sdm845_desc = { + .config = &aoss_sdm845_regmap_config, + .resets = aoss_sdm845_resets, + /* Wait 6 32kHz sleep cycles for reset */ + .delay = 200, + .num_resets = ARRAY_SIZE(aoss_sdm845_resets), +}; + +static struct qcom_aoss_reset_data *to_qcom_aoss_reset_data( + struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct qcom_aoss_reset_data, rcdev); +} + +static int qcom_aoss_control_assert(struct reset_controller_dev *rcdev, + unsigned long idx) +{ + struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev); + const struct qcom_aoss_reset_map *map = &data->desc->resets[idx]; + + return regmap_update_bits(data->regmap, map->reg, + BIT(map->bit), BIT(map->bit)); +} + +static int qcom_aoss_control_deassert(struct reset_controller_dev *rcdev, + unsigned long idx) +{ + struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev); + const struct qcom_aoss_reset_map *map = &data->desc->resets[idx]; + + return regmap_update_bits(data->regmap, map->reg, BIT(map->bit), 0); +} + +static int qcom_aoss_control_reset(struct reset_controller_dev *rcdev, + unsigned long idx) +{ + struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev); + int ret; + + ret = qcom_aoss_control_assert(rcdev, idx); + if (ret) + return ret; + + udelay(data->desc->delay); + + return qcom_aoss_control_deassert(rcdev, idx); +} + +static const struct reset_control_ops qcom_aoss_reset_ops = { + .reset = qcom_aoss_control_reset, + .assert = qcom_aoss_control_assert, + .deassert = qcom_aoss_control_deassert, +}; + +static int qcom_aoss_reset_probe(struct platform_device *pdev) +{ + struct qcom_aoss_reset_data *data; + struct device *dev = &pdev->dev; + const struct qcom_aoss_desc *desc; + + desc = of_device_get_match_data(dev); + if (!desc) + return -EINVAL; + + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->desc = desc; + data->regmap = syscon_node_to_regmap(dev->of_node); + if (IS_ERR(data->regmap)) { + dev_err(dev, "Unable to get aoss-reset regmap"); + return PTR_ERR(data->regmap); + } + regmap_attach_dev(dev, data->regmap, desc->config); + + data->rcdev.owner = THIS_MODULE; + data->rcdev.ops = &qcom_aoss_reset_ops; + data->rcdev.nr_resets = desc->num_resets; + data->rcdev.of_node = dev->of_node; + + return devm_reset_controller_register(dev, &data->rcdev); +} + +static const struct of_device_id qcom_aoss_reset_of_match[] = { + { .compatible = "qcom,aoss-reset-sdm845", .data = &aoss_sdm845_desc }, + {} +}; + +static struct platform_driver qcom_aoss_reset_driver = { + .probe = qcom_aoss_reset_probe, + .driver = { + .name = "qcom_aoss_reset", + .of_match_table = qcom_aoss_reset_of_match, + }, +}; + +builtin_platform_driver(qcom_aoss_reset_driver); + +MODULE_DESCRIPTION("Qualcomm AOSS Reset Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/include/dt-bindings/reset/qcom,aoss-sdm845.h b/include/dt-bindings/reset/qcom,aoss-sdm845.h new file mode 100644 index 0000000..e9b38fc --- /dev/null +++ b/include/dt-bindings/reset/qcom,aoss-sdm845.h @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_RESET_AOSS_SDM_845_H +#define _DT_BINDINGS_RESET_AOSS_SDM_845_H + +#define AOSS_CC_MSS_RESTART 0 +#define AOSS_CC_CAMSS_RESTART 1 +#define AOSS_CC_VENUS_RESTART 2 +#define AOSS_CC_GPU_RESTART 3 +#define AOSS_CC_DISPSS_RESTART 4 +#define AOSS_CC_WCSS_RESTART 5 +#define AOSS_CC_LPASS_RESTART 6 + +#endif
Add reset controller driver for Qualcomm SDM845 SoC to control reset signals provided by AOSS for Modem, Venus ADSP, GPU, Camera, Wireless, Display subsystem Signed-off-by: sibis <sibis@codeaurora.org> --- .../devicetree/bindings/reset/qcom,aoss-reset.txt | 54 ++++++++ drivers/reset/Kconfig | 10 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-qcom-aoss.c | 151 +++++++++++++++++++++ include/dt-bindings/reset/qcom,aoss-sdm845.h | 17 +++ 5 files changed, 233 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt create mode 100644 drivers/reset/reset-qcom-aoss.c create mode 100644 include/dt-bindings/reset/qcom,aoss-sdm845.h