From patchwork Wed Mar 14 09:21:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 10281735 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 19C1860211 for ; Wed, 14 Mar 2018 09:24:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0B13D287FB for ; Wed, 14 Mar 2018 09:24:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F27FE287FD; Wed, 14 Mar 2018 09:24:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9954E287FB for ; Wed, 14 Mar 2018 09:24:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752081AbeCNJWX (ORCPT ); Wed, 14 Mar 2018 05:22:23 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:50374 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751155AbeCNJWR (ORCPT ); Wed, 14 Mar 2018 05:22:17 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 2365C6070A; Wed, 14 Mar 2018 09:22:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521019337; bh=tULYKe2vzgpjvBGhdO2z2DL83+nGbk6oyuTG5i7U/Q0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YUdXkzFeSv7CmQAUFrSdAwszNApyYQuBaAZViTz0bxySO6PdrkipWbRIfJFqB/Eak GlTSAvZC4DPldArSqkbLCUZ7WyFjqbwvD8ZQ+UUIMhWsSm9tbRAI5TKl/J+lNnqdaQ PJrlcwVJZurQCmDy8eTzTlJS4L/UXWOUW+nUWaVs= Received: from blr-ubuntu-87.qualcomm.com (blr-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.18.19]) (using TLSv1.1 with cipher ECDHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: sibis@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 18EDC60452; Wed, 14 Mar 2018 09:22:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521019336; bh=tULYKe2vzgpjvBGhdO2z2DL83+nGbk6oyuTG5i7U/Q0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Gu3F3AL/PkVFB2JkHG+Q2dITnHNcGwZ2QDyn6x/3gqdrv9DxcrN3MhqBhH3xbXLIm +h5e0NyfME8aHRx7b900MYwe6+9fYRosOMe+lMGRro+1P8kvA0uq+/yipXTYY1mQpX GRIq++KGpvmJfdGgLDbXrKyun67xKtMvH7ner/8g= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 18EDC60452 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=sibis@codeaurora.org From: Sibi S To: bjorn.andersson@linaro.org, p.zabel@pengutronix.de, robh+dt@kernel.org Cc: linux-remoteproc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, sibis@codeaurora.org, georgi.djakov@linaro.org, jassisinghbrar@gmail.com, ohad@wizery.com, mark.rutland@arm.com, kyan@codeaurora.org, sricharan@codeaurora.org, akdwived@codeaurora.org, linux-arm-msm@vger.kernel.org, tsoni@codeaurora.org Subject: [PATCH v3 1/7] dt-bindings: reset: Add AOSS reset bindings for SDM845 SoCs Date: Wed, 14 Mar 2018 14:51:17 +0530 Message-Id: <1521019283-32212-2-git-send-email-sibis@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1521019283-32212-1-git-send-email-sibis@codeaurora.org> References: <1521019283-32212-1-git-send-email-sibis@codeaurora.org> Sender: linux-remoteproc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add SDM845 AOSS (always on subsystem) reset controller binding Signed-off-by: Sibi S --- .../devicetree/bindings/reset/qcom,aoss-reset.txt | 54 ++++++++++++++++++++++ include/dt-bindings/reset/qcom,sdm845-aoss.h | 17 +++++++ 2 files changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt create mode 100644 include/dt-bindings/reset/qcom,sdm845-aoss.h diff --git a/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt new file mode 100644 index 0000000..04dca76 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.txt @@ -0,0 +1,54 @@ +Qualcomm AOSS Reset Controller +====================================== + +This binding describes a reset-controller found on AOSS (always on subsystem) +for Qualcomm SDM845 SoCs. + +Required properties: +- compatible: + Usage: required + Value type: + Definition: must be: + "qcom,sdm845-aoss-reset" + +- reg: + Usage: required + Value type: + Definition: must specify the base address and size of the register + space. + + +- #reset-cells: + Usage: required + Value type: + Definition: must be 1; cell entry represents the reset index. + +example: + +aoss_reset: qcom,reset-controller@b2e0100 { + compatible = "qcom,sdm845-aoss-reset"; + reg = <0xc2b0000 0x20004>; + #reset-cells = <1>; +}; + + +Specifying reset lines connected to IP modules +============================================== + +Device nodes that need access to reset lines should +specify them as a reset phandle in their corresponding node as +specified in reset.txt. + +For list of all valid reset indicies see + + +Example: + +modem-pil@4080000 { + ... + + resets = <&aoss_reset AOSS_CC_MSS_RESTART>; + reset-names = "mss_restart"; + + ... +}; diff --git a/include/dt-bindings/reset/qcom,sdm845-aoss.h b/include/dt-bindings/reset/qcom,sdm845-aoss.h new file mode 100644 index 0000000..e9b38fc --- /dev/null +++ b/include/dt-bindings/reset/qcom,sdm845-aoss.h @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_RESET_AOSS_SDM_845_H +#define _DT_BINDINGS_RESET_AOSS_SDM_845_H + +#define AOSS_CC_MSS_RESTART 0 +#define AOSS_CC_CAMSS_RESTART 1 +#define AOSS_CC_VENUS_RESTART 2 +#define AOSS_CC_GPU_RESTART 3 +#define AOSS_CC_DISPSS_RESTART 4 +#define AOSS_CC_WCSS_RESTART 5 +#define AOSS_CC_LPASS_RESTART 6 + +#endif