From patchwork Mon Nov 28 13:28:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sarannya S X-Patchwork-Id: 13057520 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22318C43217 for ; Mon, 28 Nov 2022 13:29:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231773AbiK1N3S (ORCPT ); Mon, 28 Nov 2022 08:29:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54692 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231779AbiK1N3Q (ORCPT ); Mon, 28 Nov 2022 08:29:16 -0500 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B9D8F1D328; Mon, 28 Nov 2022 05:29:12 -0800 (PST) Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2ASCUDEf015466; Mon, 28 Nov 2022 13:28:57 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=HI9u2GFU8htEiR6UUb2OPsnPLZvoUE7rjEHPYn4ZC0s=; b=JAy1+g82xWeAOMwUzuSWdO2KpvLE21mtiBOtEXKcrxjuk4cEMhH95SJT0WLvCpX8qGvA 2DD9xOCcdbS+/QxEzA5BEl2pMdbFr0ezQ5zsHNRYQWE95HQlkpP2mP+k9upUEmvrNzwy 99Pn1q/s+kGoHRgwJu2QqCHPhNnixLkpveVxiMkZxZCPMv6Tx9gnagRsMKQ+CQmms3r8 4rjHqAlPe59As3U5CrtsiAAH1YbBShmCYQ8Uwzohi7gDdxF988mAWg2Fp8thaCtNr4HR kP3Go5sy3UtOZDsqiExuxdRRAJfNmGMPScnGVxWCTmCMh/l0cI4IUkqo5Sh2tEFo6G6d iQ== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3m39tg46xw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Nov 2022 13:28:57 +0000 Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 2ASDSuqr022133 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Nov 2022 13:28:56 GMT Received: from sarannya-linux.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Mon, 28 Nov 2022 05:28:52 -0800 From: Sarannya S To: , , , , CC: , , , Sarannya S , Deepak Kumar Singh , Andy Gross , Bjorn Andersson , Konrad Dybcio Subject: [PATCH V4 2/3] rpmsg: glink: Add support to handle signals command Date: Mon, 28 Nov 2022 18:58:10 +0530 Message-ID: <1669642093-20399-2-git-send-email-quic_sarannya@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1669642093-20399-1-git-send-email-quic_sarannya@quicinc.com> References: <1669642093-20399-1-git-send-email-quic_sarannya@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: KioFO9pZfHH00cUNjwkObj8YgLlA3ER0 X-Proofpoint-ORIG-GUID: KioFO9pZfHH00cUNjwkObj8YgLlA3ER0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-11-28_11,2022-11-28_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 suspectscore=0 adultscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 mlxlogscore=999 mlxscore=0 phishscore=0 impostorscore=0 priorityscore=1501 clxscore=1011 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2211280102 Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org Remote peripherals send signal notifications over glink with commandID 15. Add support to send and receive the signal command and based signals enable or disable flow control with remote host. Signed-off-by: Chris Lew Signed-off-by: Deepak Kumar Singh Signed-off-by: Sarannya S --- drivers/rpmsg/qcom_glink_native.c | 63 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/drivers/rpmsg/qcom_glink_native.c b/drivers/rpmsg/qcom_glink_native.c index 115c0a1..01d0a49 100644 --- a/drivers/rpmsg/qcom_glink_native.c +++ b/drivers/rpmsg/qcom_glink_native.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -203,9 +204,15 @@ static const struct rpmsg_endpoint_ops glink_endpoint_ops; #define RPM_CMD_TX_DATA_CONT 12 #define RPM_CMD_READ_NOTIF 13 #define RPM_CMD_RX_DONE_W_REUSE 14 +#define RPM_CMD_SIGNALS 15 #define GLINK_FEATURE_INTENTLESS BIT(1) +#define NATIVE_DTR_SIG NATIVE_DSR_SIG +#define NATIVE_DSR_SIG BIT(31) +#define NATIVE_RTS_SIG NATIVE_CTS_SIG +#define NATIVE_CTS_SIG BIT(30) + static void qcom_glink_rx_done_work(struct work_struct *work); static struct glink_channel *qcom_glink_alloc_channel(struct qcom_glink *glink, @@ -1001,6 +1008,57 @@ static int qcom_glink_rx_open_ack(struct qcom_glink *glink, unsigned int lcid) return 0; } +/** + * qcom_glink_set_flow_control() - convert a signal cmd to wire format and + * transmit + * @ept: Rpmsg endpoint for channel. + * @enable: True/False - enable or disable flow control + * + * Return: 0 on success or standard Linux error code. + */ +static int qcom_glink_set_flow_control(struct rpmsg_endpoint *ept, bool enable) +{ + struct glink_channel *channel = to_glink_channel(ept); + struct qcom_glink *glink = channel->glink; + struct glink_msg msg; + u32 sigs = 0; + + if (enable) + sigs |= NATIVE_DTR_SIG | NATIVE_RTS_SIG; + + msg.cmd = cpu_to_le16(RPM_CMD_SIGNALS); + msg.param1 = cpu_to_le16(channel->lcid); + msg.param2 = cpu_to_le32(sigs); + + return qcom_glink_tx(glink, &msg, sizeof(msg), NULL, 0, true); +} + +static int qcom_glink_handle_signals(struct qcom_glink *glink, + unsigned int rcid, unsigned int sigs) +{ + struct glink_channel *channel; + unsigned long flags; + bool enable = false; + + spin_lock_irqsave(&glink->idr_lock, flags); + channel = idr_find(&glink->rcids, rcid); + spin_unlock_irqrestore(&glink->idr_lock, flags); + if (!channel) { + dev_err(glink->dev, "signal for non-existing channel\n"); + return -EINVAL; + } + + if (!channel->ept.flow_cb) + return 0; + + if (sigs & (NATIVE_DSR_SIG | NATIVE_CTS_SIG)) + enable = true; + + channel->ept.flow_cb(channel->ept.rpdev, channel->ept.priv, enable); + + return 0; +} + static irqreturn_t qcom_glink_native_intr(int irq, void *data) { struct qcom_glink *glink = data; @@ -1065,6 +1123,10 @@ static irqreturn_t qcom_glink_native_intr(int irq, void *data) qcom_glink_handle_intent_req_ack(glink, param1, param2); qcom_glink_rx_advance(glink, ALIGN(sizeof(msg), 8)); break; + case RPM_CMD_SIGNALS: + qcom_glink_handle_signals(glink, param1, param2); + qcom_glink_rx_advance(glink, ALIGN(sizeof(msg), 8)); + break; default: dev_err(glink->dev, "unhandled rx cmd: %d\n", cmd); ret = -EINVAL; @@ -1440,6 +1502,7 @@ static const struct rpmsg_endpoint_ops glink_endpoint_ops = { .sendto = qcom_glink_sendto, .trysend = qcom_glink_trysend, .trysendto = qcom_glink_trysendto, + .set_flow_control = qcom_glink_set_flow_control, }; static void qcom_glink_rpdev_release(struct device *dev)