diff mbox

rpmsg: glink: smem: Ensure ordering during tx

Message ID 20171214201546.21942-1-bjorn.andersson@linaro.org (mailing list archive)
State Accepted, archived
Headers show

Commit Message

Bjorn Andersson Dec. 14, 2017, 8:15 p.m. UTC
Ensure the ordering of the fifo write and the update of the write index,
so that the index is not updated before the data has landed in the fifo.

Reported-by: Arun Kumar Neelakantam <aneela@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
 drivers/rpmsg/qcom_glink_smem.c | 3 +++
 1 file changed, 3 insertions(+)

Comments

Chris Lew Dec. 18, 2017, 10:09 p.m. UTC | #1
On 12/14/2017 12:15 PM, Bjorn Andersson wrote:
> Ensure the ordering of the fifo write and the update of the write index,
> so that the index is not updated before the data has landed in the fifo.
> 
> Reported-by: Arun Kumar Neelakantam <aneela@codeaurora.org>
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---

Acked-By: Chris Lew <clew@codeaurora.org>
diff mbox

Patch

diff --git a/drivers/rpmsg/qcom_glink_smem.c b/drivers/rpmsg/qcom_glink_smem.c
index 057528e23d3a..892f2b92a4d8 100644
--- a/drivers/rpmsg/qcom_glink_smem.c
+++ b/drivers/rpmsg/qcom_glink_smem.c
@@ -183,6 +183,9 @@  static void glink_smem_tx_write(struct qcom_glink_pipe *glink_pipe,
 	if (head >= pipe->native.length)
 		head -= pipe->native.length;
 
+	/* Ensure ordering of fifo and head update */
+	wmb();
+
 	*pipe->head = cpu_to_le32(head);
 }